Memory device

Patent metadata

Field	Value
Publication number	US-2021257366-A1
Application number	US-202016939842-A
Country	US
Kind code	A1
Filing date	Jul 27, 2020
Priority date	Feb 19, 2020
Publication date	Aug 19, 2021
Grant date	—

Abstract

A memory cell includes: a bit line and a plate line that are spaced apart from each other and vertically oriented in a first direction; a transistor including an active layer, the active layer being laterally oriented in a second direction, intersecting with the bit line; a capacitor laterally oriented in the second direction between the active layer and the plate line; and a word line laterally oriented in a third direction, intersecting with the bit line and the active layer, wherein the word line is embedded in the active layer.

First claim

What is claimed is:

1 . A memory cell, comprising:
a bit line and a plate line that are spaced apart from each other and vertically oriented in a first direction; a transistor including an active layer, the active layer being laterally oriented in a second direction, intersecting with the bit line; a capacitor laterally oriented in the second direction between the active layer and the plate line; and a word line laterally oriented in a third direction, intersecting with the bit line and the active layer, wherein the word line is embedded in the active layer.

2 . The memory cell of claim 1 , wherein the active layer includes a through portion extending in the third direction, and the word line is positioned in the through portion.

3 . The memory cell of claim 1 , wherein the active layer includes:
a first active cylinder coupled to the bit line; a second active cylinder coupled to the capacitor; and a pair of plate portions laterally oriented between the first active cylinder and the second active cylinder.

4 . The memory cell of claim 3 , wherein the first active cylinder, the second active cylinder, and the pair of the plate portions are positioned in a lateral arrangement in the second direction.

5 . The memory cell of claim 3 , wherein the word line includes:
a buried body portion positioned between the pair of the plate portions and extending in the third direction; a first buried portion extending from one side of the buried body portion and buried in a cylinder-shaped interior of the first active cylinder; and a second buried portion extending from another side of the buried body portion and buried in a cylinder-shaped interior of the second active cylinder.

6 . The memory cell of claim 3 , wherein the first active cylinder and the second active cylinder are positioned at the same level and have laterally oriented cylinder shapes that are laterally spaced apart in the second direction.

7 . The memory cell of claim 3 , wherein a lateral length of the first active cylinder in the second direction and a lateral length of the second active cylinder in the second direction are different.

8 . The memory cell of claim 3 , wherein the first active cylinder includes a laterally oriented first recess, and
the second active cylinder includes a laterally oriented second recess, and the laterally oriented first recess and laterally oriented second recess face each other in the second direction.

9 . The memory cell of claim 1 , further comprising:
a gate dielectric layer formed between the word line and the active layer.

10 . The memory cell of claim 1 , wherein the capacitor includes:
a storage node coupled to the transistor; a plate node coupled to the plate line; and a dielectric material between the storage node and the plate node, and the storage node, the dielectric material, and the plate node are positioned in a lateral arrangement in the second direction.

11 . The memory cell of claim 10 , wherein the plate node includes:
an internal node laterally oriented from the plate line and extending into a cylinder-shaped interior of the storage node; and a plurality of external nodes that are laterally oriented from the plate line and surrounding a cylinder-shaped exterior of the storage node.

12 . The memory cell of claim 11 , wherein the external nodes include:
first and second external nodes positioned on the cylinder-shaped exterior of the storage node in the first direction; and third and fourth external nodes positioned on the cylinder-shaped exterior of the storage node in the third direction, and lateral lengths of the first external node and the second external node are shorter than lateral lengths of the third external node and the fourth external node.

13 . The memory cell of claim 12 , wherein a lateral length of the first external node and a lateral length of the second external node are the same, and
a lateral length of the third external node and a lateral length of the fourth external node are the same.

14 . The memory cell of claim 1 , further comprising:
a first source/drain region formed between the active layer and the bit line; and a second source/drain region formed between another side of the active layer and the capacitor.

15 . The memory cell of claim 1 , wherein the active layer includes:
a vertical edge side wall between the capacitor and the word line; a pair of plate portions extending from upper and lower portions of the vertical edge side wall; and an open side wall between the word line and bit line.

16 . The memory cell of claim 15 , further comprising:
a first source/drain region coupled to the bit line while filling the open side wall of the active layer; a second source/drain region selectively grown from the vertical edge side wall of the active layer and coupled to the capacitor; and an Ohmic contact layer between the first source/drain region and the bit line.

17 . A memory device, comprising:
a memory cell array including a plurality of memory cells that are vertically arrayed in a first direction, wherein each of the memory cells includes:
a bit line and a plate line that are spaced apart from each other and vertically oriented in the first direction;
a transistor including an active layer, the active layer being laterally oriented in a second direction, intersecting with the bit line, wherein the transistor includes a first active cylinder, a second active cylinder, and a pair of plate portions that are laterally oriented between the first active cylinder and the second active cylinder;
a word line laterally oriented in a third direction, while penetrating between the pair of the plate portions of the active layer; and
a capacitor laterally oriented in the second direction TO between the active layer and the plate line.

18 . The memory device of claim 17 , wherein the word line includes:
a buried body portion extending in the third direction while penetrating between the pair of the plate portions; a first buried portion laterally extending in the second direction from one side of the buried body portion and buried in the first active cylinder; and a second buried portion laterally extending in the second direction from another side of the buried body portion and buried in the second active cylinder.

19 . The memory device of claim 17 , further comprising:
a peripheral circuit unit positioned below the memory cell array and including at least one control circuit for controlling the memory cells.

20 . The memory device of claim 17 , further comprising:
a peripheral circuit unit positioned over the memory cell array and including at least one control circuit for controlling the memory cells.

Assignees

• Sk Hynix Inc

Inventors

• Lee Ki Hong

Classifications

• H10D62/121

  oriented parallel to substrates · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D30/6713

  characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes · CPC title

• H10D1/714 Primary

  having horizontal extensions · CPC title