Stacked nanosheet devices with matched threshold voltages for nfet/pfet

Patent metadata

Field	Value
Publication number	US-2023163127-A1
Application number	US-202117455941-A
Country	US
Kind code	A1
Filing date	Nov 22, 2021
Priority date	Nov 22, 2021
Publication date	May 25, 2023
Grant date	—

Abstract

A semiconductor device includes a lower nano device that includes a plurality of stacked first nano sheets, where the first nano sheets are spaced apart from each other a first distance. An upper nano device that includes a plurality of stacked second nano sheets, where the second nano sheets are spaced apart from each other a second distance, where the second distance is larger than the first distance.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a lower nano device that includes a plurality of stacked first nano sheets, wherein the first nano sheets are spaced apart from each other a first distance; an upper nano device that includes a plurality of stacked second nano sheets, wherein the second nano sheets are spaced apart from each other a second distance, wherein the second distance is larger than the first distance.

2 . The semiconductor device of claim 1 , wherein the lower nano device further comprises:
a first metal layer located below and above each of the plurality of stacked first nano sheets, wherein the first metal layer has a first thickness T 1 .

3 . The semiconductor device of claim 2 , wherein the first metal layer is comprised of TiN.

4 . The semiconductor device of claim 2 , where the upper nano device further comprises:
a second metal layer located below and above each of the plurality of stacked second nano sheets; a first metal liner located around the second metal layer, wherein the second metal layer and the first metal liner have a combined thickness T 2 .

5 . The semiconductor device of claim 4 , wherein the first metal liner is comprised of TiN, wherein the second metal layer is comprised of TiC or TiAlC.

6 . The semiconductor device of claim 4 , wherein the combined thickness T 2 is greater than the first thickness T 1 .

7 . The semiconductor device of claim 1 , further comprising:
a top spacer located on top of the upper nano device, wherein the top spacer has a U-shape.

8 . The semiconductor device of claim 7 , further comprising:
a first metal liner is located on the inside surface of the top spacer.

9 . The semiconductor device of claim 8 , further comprising:
a second metal liner is located on the first metal liner located on the inside surface of the top spacer.

10 . The semiconductor device of claim 9 , further comprising:
a metal cap located on top of the second metal liner, wherein the metal cap is located within the U-shape top spacer.

11 . The semiconductor device of claim 10 , wherein the first metal liner is comprised of TiN, the second metal liner is comprised of TiC or TiAlC, and the metal cap is comprised of Tungsten (W).

12 . A semiconductor device comprising:
a lower nano device that includes a plurality of stacked first nano sheets and a PFET material located around the plurality of stacked first nano sheets, wherein the first nano sheets are spaced apart from each other a first distance; an upper nano device that includes a plurality of stacked second nano sheets a NFET material located around the plurality of stacked second nano sheets, wherein the second nano sheets are spaced apart from each other a second distance, wherein the second distance is larger than the first distance.

13 . The semiconductor device of claim 12 , wherein the lower nano device further comprises:
a first metal layer located below and above each of the plurality of stacked first nano sheets, wherein the first metal layer has a first thickness T 1 .

14 . The semiconductor device of claim 13 , wherein the first metal layer is comprised of TiN.

15 . The semiconductor device of claim 13 , where the upper nano device further comprises:
a second metal layer located below and above each of the plurality of stacked second nano sheets; a first metal liner located around the second metal layer, wherein the second metal layer and the first metal liner have a combined thickness T 2 .

16 . The semiconductor device of claim 15 , wherein the first metal liner is comprised of TiN, wherein the second metal layer is comprised of TiC or TiAlC.

17 . The semiconductor device of claim 15 , wherein the combined thickness T 2 is greater than the first thickness T 1 .

18 . A method manufacturing a semiconductor device, the method comprising:
forming a lower nano device that includes a plurality of stacked first nano sheets and a plurality of first sacrificial layers, wherein a first sacrificial layer is located above and/or below each of the first nano sheets, wherein the each of the plurality of first sacrificial layers has a first thickness T 1 ; forming an upper nano device that includes a plurality of stacked second nano sheets and a plurality of second sacrificial layers, wherein a second sacrificial layer is located above and/or below each of the second nano sheets, wherein the each of the plurality of second sacrificial layers has a second thickness T 2 , wherein the second thickness T 2 is greater than the first thickness T 1 .

19 . The method of claim 18 , further comprising:
selectively removing the plurality of first sacrificial layers and the plurality of second sacrificial layers; forming a first metal layer in a space created by removing the plurality of first sacrificial layers and the plurality of second sacrificial layers, wherein the first metal layer pinches off space created by the removal of the plurality of first sacrificial layers, wherein the first metal layer forms a first metal liner in the space created by the removal of the plurality of second sacrificial layers.

20 . The method of claim 19 , further comprising:
forming a second metal layer on top of the first metal liner to pinch off the space created by the removal of the plurality of second sacrificial layers.

Assignees

• IBM

Inventors

• Wu Heng
• Frougier Julien
• Zhang Chen
• Liu Zuoguang
• Xie Ruilong
• Reznicek Alexander

Classifications

• H10P14/3452

  Microstructure · CPC title

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10D84/0177

  the gate conductors having different materials or different implants · CPC title

• H10D84/0167

  Manufacturing their channels · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title