Display device having a clock training with a plurality of signal levels and driving method thereof

Patent metadata

Field	Value
Publication number	US-2023162689-A1
Application number	US-202217815590-A
Country	US
Kind code	A1
Filing date	Jul 28, 2022
Priority date	Nov 19, 2021
Publication date	May 25, 2023
Grant date	—

Abstract

A display device includes a timing controller for supplying a clock training signal through a data clock signal line in a first period of one frame period, and supplying image data through the data clock signal line in a second period of the one frame period, a data driver for generating a clock signal, based on the clock training signal in a clock training period in the first period, and generating a data signal, based on the clock signal and the image data in the second period, and a pixel unit for displaying an image, based on the data signal. The clock training signal includes a plurality of signal levels, and the data driver determines the clock training period, based on the signal levels of the clock training signal.

First claim

1 . A display device comprising:
a timing controller configured to supply a clock training signal through a data clock signal line in a first period of one frame period, and supply image data through the data clock signal line in a second period of the one frame period; a data driver configured to generate a clock signal, based on the clock training signal in a clock training period in the first period, and generate a data signal, based on the clock signal and the image data in the second period; and a pixel unit configured to display an image, based on the data signal, wherein the clock training signal includes a plurality of signal levels, and wherein the data driver determines the clock training period, based on the signal levels of the clock training signal, wherein the clock training signal includes a first bit and a second bit, which correspond to each of the signal levels, and wherein the data driver determines the clock training period, based on the first bit of the clock training signal.

2 . (canceled)

3 . The display device of claim 1 , wherein the first bit of the clock training signal has a first value in the clock training period in the first period, and has a second value in a period except the clock training period in the first period.

4 . The display device of claim 3 , wherein the data driver determines, as the clock training period, a period in which the first bit of the clock training signal has the first value in the first period.

5 . The display device of claim 3 , wherein the data driver determines, as the clock training period, a period between times at which the first bit of the clock training signal is changed in the first period.

6 . The display device of claim 3 , wherein the data driver generates the clock signal, corresponding to the second bit of the clock training signal in the clock training period.

7 . A display device of claim 1 , comprising:
a timing controller configured to supply a clock training signal through a data clock signal line in a first period of one frame period, and supply image data through the data clock signal line in a second period of the one frame period; a data driver configured to generate a clock signal, based on the clock training signal in a clock training period in the first period, and generate a data signal, based on the clock signal and the image data in the second period; and a pixel unit configured to display an image, based on the data signal, wherein the clock training signal includes a plurality of signal levels, and wherein the data driver determines the clock training period, based on the signal levels of the clock training signal, wherein the clock training signal has a predetermined signal level in sub-periods different from the clock training period in the first period.

8 . The display device of claim 7 , wherein the data driver extracts the sub-periods, based on the predetermined signal level, and determines a period between the sub-periods as the clock training period.

9 . The display device of claim 7 , wherein the sub-periods include a first sub-period and a second sub-period, and
wherein the clock training signal has one signal level among a first signal level, a second signal level greater than the first signal level, a third signal level greater than the second signal level, and a fourth signal level greater than the third signal level.

10 . The display device of claim 9 , wherein the clock training signal has the first signal level in the first sub-period and the second sub-period.

11 . The display device of claim 9 , wherein the clock training signal:
has a signal level which sequentially decreases from the third signal level to the first signal level in the first sub-period; and has a signal level which sequentially increases from the first signal level to the third signal level in the second sub-period.

12 . The display device of claim 9 , wherein the clock training signal:
has the second signal level or the third signal level in the clock training period; and has the fourth signal level in a period except the first sub-period, the second period, and the clock training period in the first period.

13 . The display device of claim 12 , wherein the data driver generates the clock signal, corresponding to the clock training signal having the second signal level or the third signal level in the clock training period.

14 . The display device of claim 1 , wherein the clock training signal includes 2-bit signal levels.

15 . The display device of claim 1 , wherein the data driver includes a plurality of data driving circuits,
wherein the data clock signal line includes a plurality of sub-data clock signal lines, and wherein the timing controller is connected to the data driving circuits respectively through the plurality of sub-data clock signal lines.

16 . A method of driving a display device, the method comprising:
supplying a clock training signal including a plurality of signal levels through a data clock signal line in a first period of one frame period; supplying image data through the data clock signal line in a second period of the one frame period; determining a clock training period in the first period, based on the signal levels of the clock training signal; generating a clock signal, based on the clock training signal in the clock training period in the first period; generating a data signal, based on the clock signal and the image data in the second period; and displaying an image, based on the data signal, wherein the clock training signal includes a first bit and a second bit, which correspond to each of the signal levels, and wherein, in the determining of the clock training period, the clock training period is determined based on the first bit of the clock training signal.

17 . (canceled)

18 . The method of claim 16 , wherein, in the generating of the clock signal, the clock signal is generated corresponding to the second bit of the clock training signal.

19 . The method of claim 16 , wherein the clock training signal has a predetermined signal level in sub-periods different from the clock training period in the first period.

20 . The method of claim 19 , wherein, in the determining of the clock training period, the sub-periods are extracted based on the predetermined signal level, and a period between the sub-periods is determined as the clock training period.

21 . A display device comprising:
a timing controller configured to supply a clock training signal through a data clock signal line in a first period of one frame period, and supply image data through the data clock signal line in a second period of the one frame period; a data driver configured to generate a clock signal, based on the clock training signal in a clock training period in the first period, and generate a data signal, based on the clock signal and the image data in the second period; and a pixel unit configured to display an image, based on the data signal, wherein the clock training signal includes first, second, and third signal levels that are different from one another, and wherein the data driver determines a start of the clock training period by detecting the clock training signal transitioning from the third signal level to one of the first and second signal levels.

Assignees

• Samsung Display Co Ltd

Inventors

• Park Chae Hee
• Kim Jong Soo
• Kim Heen Dol
• Lee Ji Ye
• Jung Young Suk

Classifications

• G09G3/3275 Primary

  Details of drivers for data electrodes · CPC title

• G09G3/2092

  Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165) · CPC title

• G09G3/2014

  by modulation of the duration of a single pulse during which the logic level remains constant · CPC title

• G09G3/2077

  by a combination of two or more gradation control methods · CPC title

• G09G3/2011

  by amplitude modulation · CPC title