Integrated circuit and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2023142050-A1
Application number	US-202217984417-A
Country	US
Kind code	A1
Filing date	Nov 10, 2022
Priority date	Nov 11, 2021
Publication date	May 11, 2023
Grant date	—

Abstract

An integrated circuit including a plurality of stacked metal layers and a method of manufacturing the integrated circuit are provided. The method includes: providing a plurality of standard cells, each of which includes cell patterns respectively formed on the plurality of metal layers; and forming, on a particular metal layer among the plurality of metal layers which includes patterns extending in a first direction that are respectively formed on a plurality of tracks that are spaced apart from each other in a second direction, an additional pattern between adjacent patterns formed on a particular track of the plurality of tracks based on an interval between the adjacent patterns exceeding a reference value.

First claim

1 . A method of manufacturing an integrated circuit comprising a plurality of metal layers, which are stacked, the method comprising:
providing a plurality of standard cells, each of which comprises cell patterns respectively formed on the plurality of metal layers; and forming, on a particular metal layer among the plurality of metal layers which includes patterns extending in a first direction that are respectively formed on a plurality of tracks that are spaced apart from each other in a second direction, an additional pattern between adjacent patterns formed on a particular track of the plurality of tracks based on an interval between the adjacent patterns exceeding a reference value.

2 . The method of claim 1 , wherein the forming of the additional pattern comprises forming a dummy pattern over a first standard cell and a second standard cell adjacent to each other among the plurality of standard cells, the dummy pattern being electrically separated from other patterns.

3 . The method of claim 2 , wherein each of the first standard cell and the second standard cell comprises a logic cell.

4 . The method of claim 1 , wherein the forming the additional pattern comprises forming an extension pattern extending from a cell pattern of a first standard cell among the plurality of standard cells.

5 . The method of claim 4 , wherein the forming the extension pattern comprises forming the extension pattern over the first standard cell and a second standard cell adjacent to the first standard cell.

6 . The method of claim 4 , further comprising forming a via which connects the extension pattern to a pattern of another layer of the plurality of metal layers.

7 . The method of claim 1 , wherein the adjacent patterns formed on an identical track among the plurality of tracks are spaced apart from each other by at least one designated value.

8 . (canceled)

9 . The method of claim 1 , wherein the plurality of standard cells are electrically connected to a plurality of power rails extending in the first direction.

10 . The method of claim 1 , wherein the plurality of standard cells are electrically connected to a plurality of power rails extending in the second direction.

11 . (canceled)

12 . An integrated circuit comprising a plurality of metal layers, which are stacked, the integrated circuit comprising:
a first logic cell and a second logic cell, each comprising cell patterns respectively formed on the plurality of metal layers, wherein a particular metal layer among the plurality of metal layers comprises patterns extending in a first direction and a plurality of first tracks spaced apart from each other in a second direction; and a dummy pattern formed on a particular track of the plurality of first tracks over the first logic cell and the second logic cell in the particular metal layer, wherein the dummy pattern is electrically separated from other patterns on the particular metal layer, wherein patterns are respectively formed on each of the plurality of first tracks.

13 . The integrated circuit of claim 12 , wherein the plurality of metal layers are provided on a substrate, and
wherein among the plurality of metal layers, the particular metal layer is closest to the substrate.

14 - 15 . (canceled)

16 . The integrated circuit of claim 12 , wherein the first logic cell and the second logic cell have an identical cell height in the first direction.

17 . (canceled)

18 . The integrated circuit of claim 12 , wherein the first logic cell and the second logic cell have different cell heights in the first direction,
wherein the plurality of metal layers are provided on a substrate, wherein, a lower metal layer, among the plurality of metal layers, provided between the substrate and the particular metal layer, comprises patterns extending in the second direction and a plurality of second tracks spaced apart from each other in the first direction, and wherein, among the plurality of second tracks, a number of second tracks passing through a cell boundary of the first logic cell is different from a number of second tracks passing through a cell boundary of the second logic cell.

19 . The integrated circuit of claim 12 , wherein the adjacent patterns are spaced apart from each other by at least one designated value.

20 . The integrated circuit of claim 12 , further comprising an extension pattern formed on the particular metal layer, and extending from a cell pattern of the first logic cell.

21 . (canceled)

22 . An integrated circuit comprising a plurality of metal layers, which are stacked, the integrated circuit comprising:
a first standard cell and a second standard cell, each comprising cell patterns respectively formed on the plurality of metal layers, wherein a particular metal layer among the plurality of metal layers comprises patterns extending in a first direction and a plurality of first tracks spaced apart from each other in a second direction; and an extension pattern formed on a particular track of the plurality of first tracks over the first standard cell and the second standard cell in the particular metal layer, wherein the extension pattern extends from a cell pattern of the first standard cell, wherein adjacent patterns are spaced apart from each other by at least one designated value.

23 . The integrated circuit of claim 22 , wherein the plurality of metal layers are provided on a substrate, and
wherein among the plurality of metal layers, the particular metal layer is closest to the substrate.

24 . The integrated circuit of claim 22 , wherein the first standard cell and the second standard cell have an identical cell height in the first direction.

25 . The integrated circuit of claim 22 , wherein the first standard cell and the second standard cell have different cell heights from each other in the first direction.

26 . (canceled)

27 . The integrated circuit of claim 22 , further comprising a dummy pattern formed on the first standard cell and electrically from other patterns on the particular metal layer.

28 - 29 . (canceled)

Assignees

• Samsung Electronics Co Ltd

Inventors

• You Hyeongyu
• Do Jungho
• Park Sangdo
• Seo Jaewoo
• YU Jisu
• Jeong Minjae
• Cho Dayeon

Classifications

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W20/067 Primary

  by modifying the pattern of conductive parts · CPC title

• H10D89/10 Primary

  Integrated device layouts · CPC title

• H10D1/714

  having horizontal extensions · CPC title

• H10D1/043

  using patterning processes to form electrode extensions, e.g. etching · CPC title