Silicon carbide semiconductor device and power converter

Patent metadata

Field	Value
Publication number	US-2023133459-A1
Application number	US-202017918115-A
Country	US
Kind code	A1
Filing date	May 29, 2020
Priority date	May 29, 2020
Publication date	May 4, 2023
Grant date	—

Abstract

Fluctuations in device characteristics are suppressed by suppressing local occurrences of a large current through a body diode of a field-effect transistor. A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate, a semiconductor layer formed on the upper surface of the silicon carbide semiconductor substrate, and a backside electrode formed on the lower surface of the silicon carbide semiconductor substrate. A region in which electric resistivity takes a first value is regarded as a first resistance region, and a region where the electric resistivity takes a second value greater than the first value is regarded as a second resistance region. The second resistance region extends across a region boundary, i.e., the boundary between the active region and the termination region, in plan view.

First claim

1 . A silicon carbide semiconductor device comprising:
a silicon carbide semiconductor substrate of a first conductivity type; a semiconductor layer of the first conductivity type formed on an upper surface of the silicon carbide semiconductor substrate; and a backside electrode formed on a lower surface of the silicon carbide semiconductor substrate, wherein a region in which a field-effect transistor is formed in a surface layer of the semiconductor layer and on an upper surface of the semiconductor layer is regarded as an active region, a region that surrounds the active region in plan view is regarded as a termination region, a region in which electric resistivity between the silicon carbide semiconductor substrate and the backside electrode takes a first value is regarded as a first resistance region, a region in which the electric resistivity between the silicon carbide semiconductor substrate and the backside electrode takes a second value greater than the first value is regarded as a second resistance region, and the second resistance region is a region that extends across a region boundary in plan view, the region boundary being a boundary between the active region and the termination region.

2 . The silicon carbide semiconductor device according to claim 1 , wherein
a distance Di in plan view between the region boundary and an edge of the second resistance region that is included in the active region in plan view satisfies T≤Di≤T×10, and a distance Do between the region boundary and an edge of the second resistance region that is included in the termination region in plan view satisfies T≤Do, where T is a total thickness of the silicon carbide semiconductor substrate and the semiconductor layer.

3 . The silicon carbide semiconductor device according to claim 1 , wherein
the second resistance region is a region that extends over a whole of the termination region.

4 . The silicon carbide semiconductor device according to claim 1 , wherein
contact resistivity between the silicon carbide semiconductor substrate and the backside electrode in the second resistance region is higher than contact resistivity between the silicon carbide semiconductor substrate and the backside electrode in the first resistance region.

5 . The silicon carbide semiconductor device according to claim 1 , wherein
in the second resistance region, ohmic contact is not established between the silicon carbide semiconductor substrate and the backside electrode.

6 . The silicon carbide semiconductor device according to claim 1 , wherein
in the first resistance region, ohmic contact is established by silicide formed between the silicon carbide semiconductor substrate and the backside electrode.

7 . The silicon carbide semiconductor device according to claim 1 , further comprising:
an impurity region of the second conductivity type formed in a surface layer on a lower surface side of the silicon carbide semiconductor substrate and overlapping with the second resistance region in plan view.

8 . The silicon carbide semiconductor device according to claim 7 , wherein
the impurity region includes: a first impurity layer; and a second impurity layer having a different impurity concentration from an impurity concentration of the first impurity layer.

9 . The silicon carbide semiconductor device according to claim 1 , wherein
the backside electrode includes: a first metal layer provided overlapping with the first resistance region; and a second metal layer provided overlapping with the second resistance region and containing a different type of metal from a metal of the first metal layer.

10 . The silicon carbide semiconductor device according to claim 1 , wherein
electric resistivity between the silicon carbide semiconductor substrate and the backside electrode changes continuously from the first resistance region to the second resistance region.

11 . A silicon carbide semiconductor device comprising:
a silicon carbide semiconductor substrate; a semiconductor layer formed on an upper surface of the silicon carbide semiconductor substrate; and a backside electrode formed on part of a lower surface of the silicon carbide semiconductor substrate, wherein a region in which a field-effect transistor is formed in a surface layer of the semiconductor layer and on an upper surface of the semiconductor layer is regarded as an active region, a region that surrounds the active region in plan view is regarded as the termination region, a region in which the backside electrode is formed in plan view is regarded as a first region, a region in which the backside electrode is not formed in plan view is regarded as a second region, and the second region is a region that extends across a region boundary in plan view, the region boundary being a boundary between the active region and the termination region.

12 . The silicon carbide semiconductor device according to claim 11 , wherein
a distance Di in plan view between the region boundary and an edge of the second region that is included in the active region in plan view satisfies T≤Di≤T×10, and a distance Do in plan view between the region boundary and an edge of the second region that is included in the termination region in plan view satisfies T≤Do when T is a total thickness of the silicon carbide semiconductor substrate and the semiconductor layer.

13 . The silicon carbide semiconductor device according to claim 11 , wherein
the second region is a region that extends over a whole of the termination region.

14 . A power converter comprising:
a conversion circuit that includes the silicon carbide semiconductor device according to claim 1 and converts and outputs input electric power; a driving circuit that outputs a driving signal for driving the silicon carbide semiconductor device to the silicon carbide semiconductor device; and a control circuit that outputs a control signal for controlling the driving circuit to the driving circuit.

Assignees

• Mitsubishi Electric Corp

Inventors

• Tanaka Takanori
• NAGAHISA Yuichi
• Kawabata Naoyuki
• Amishiro Hiroyuki

Classifications

• H10D64/0115

  to silicon carbide · CPC title

• H10D30/0291

  of vertical DMOS [VDMOS] FETs · CPC title

• H10D64/252

  for vertical or pseudo-vertical devices · CPC title

• H10D62/8325

  Silicon carbide · CPC title

• H10D64/62

  Electrodes ohmically coupled to a semiconductor · CPC title