Power Semiconductor Device and Method

Patent metadata

Field	Value
Publication number	US-2020357883-A1
Application number	US-202016868314-A
Country	US
Kind code	A1
Filing date	May 6, 2020
Priority date	May 7, 2019
Publication date	Nov 12, 2020
Grant date	—

Abstract

A power semiconductor device includes an active region having a total volume with a central volume forming at least 20% of the total volume, a peripheral volume forming at least 20% of the total volume and surrounding the central volume, and an outermost peripheral volume forming at least 5% of the total volume and surrounding the peripheral volume. The peripheral volume has a constant lateral distance from an edge termination region. A first doped semiconductor region is electrically connected with a first load terminal at a semiconductor body frontside. A second doped semiconductor region is electrically connected with a second load terminal at a semiconductor body backside. The first and/or second doped semiconductor region has: a central portion extending into the central volume and having a central average dopant dose; and a peripheral portion extending into the peripheral volume and having a peripheral average dopant dose.

First claim

What is claimed is:

1 . A power semiconductor device, comprising:
an active region with at least one power cell, wherein the active region has a total volume, the total volume comprising:
a central volume forming at least 20% of the total volume;
a peripheral volume forming at least 20% of the total volume and surrounding the central volume; and
an outermost peripheral volume forming at least 5% of the total volume and surrounding the peripheral volume;
an edge termination region surrounding the outermost peripheral volume of the active region, wherein the peripheral volume has a constant lateral distance from the edge termination region; a semiconductor body having a frontside and a backside, wherein the semiconductor body forms a part of the active region and a part of the edge termination region; a first load terminal at the semiconductor body frontside and a second load terminal at the semiconductor body backside; a first doped semiconductor region formed in the semiconductor body and electrically connected with the first load terminal; and a second doped semiconductor region formed in the semiconductor body and electrically connected with the second load terminal, wherein at least one of the first doped semiconductor region and the second doped semiconductor region comprises:
a central portion extending into the central volume of the active region and having a central average dopant dose; and
a peripheral portion extending into the peripheral volume of the active region and having a peripheral average dopant dose,
wherein the central average dopant dose is lower than the peripheral average dopant dose by at least 5%.

2 . The power semiconductor device of claim 1 , wherein the semiconductor body in the active region is configured to conduct a load current between the first load terminal and the second load terminal, and/or wherein the power semiconductor device is a power semiconductor diode, or an IGBT or a MOSFET.

3 . The power semiconductor device of claim 1 , wherein the second doped semiconductor region joins into a fourth doped semiconductor region, and wherein the fourth doped semiconductor region is of a same conductivity type as the second doped semiconductor region and extends along the backside within the edge termination region.

4 . The power semiconductor device of claim 3 , wherein the central average dopant dose of the second doped semiconductor region is at least four times as large as the average dopant dose of the fourth doped semiconductor region in the edge termination region.

5 . A power semiconductor device, comprising:
an active region with at least one power cell, wherein the active region has a total volume, the total volume having a central volume forming at least 80% of the total volume; a peripheral volume surrounding the central volume; an edge termination region arranged external of the active region and surrounding the peripheral volume; a semiconductor body having a frontside and a backside, wherein the semiconductor body forms a part of each of the active region, the peripheral volume and the edge termination region, wherein the semiconductor body has a total thickness along a vertical direction between the frontside and the backside, wherein the peripheral volume has a lateral extension amounting to at least half of the total semiconductor body thickness; a first load terminal at the semiconductor body frontside and a second load terminal at the semiconductor body backside; a first doped semiconductor region formed in the semiconductor body and electrically connected with the first load terminal; and a second doped semiconductor region formed in the semiconductor body and electrically connected with the second load terminal, wherein the second doped semiconductor region comprises:
a central portion extending into the central volume of the active region and having a central average dopant dose;
a peripheral portion extending into the peripheral volume and having a peripheral average dopant dose with, along the lateral extension of the peripheral volume, a negative gradient in a lateral direction towards the edge termination region; and
an edge portion extending into the edge termination region and having a peripheral average dopant dose, the edge average dopant dose being lower than the central average dopant dose.

6 . The power semiconductor device of claim 5 , wherein the semiconductor body in the active region is configured to conduct a load current between the first load terminal and the second load terminal, and/or wherein the power semiconductor device is an IGBT or a MOSFET.

7 . The power semiconductor device of claim 5 , wherein both the first doped semiconductor region and the second doped semiconductor region are configured to contribute in forming a load current path.

8 . The power semiconductor device of claim 7 , wherein the peripheral average dopant dose is greater than the central average dopant dose.

9 . The power semiconductor device of claim 5 , wherein the negative gradient of the peripheral average dopant dose along the lateral is smaller than 5% per 1 μm.

10 . The power semiconductor device of claim 5 , wherein the respective dopant dose is defined by the dopant concentration integrated along a vertical direction pointing from the first load terminal to the second load terminal.

11 . The power semiconductor device of claim 10 , wherein the respective average dopant dose is defined by the dopant dose averaged along a distance of at least 10 μm in a lateral direction perpendicular to the vertical direction and pointing from the central volume to the edge termination region.

12 . The power semiconductor device of claim 11 , wherein the respective average dopant dose is defined by the dopant dose averaged along the total lateral extension of the respective region, or, respectively, volume, in the lateral direction.

13 . The power semiconductor device of claim herein in a vertical cross-section of the power semiconductor device:
the first load terminal and the first doped semiconductor region laterally overlap with each other; and a transition between the first load terminal and the first doped semiconductor region along the vertical direction is electrically conductive along at least 75% of the total lateral extension of the peripheral volume in the vertical cross-section.

14 . The power semiconductor device of claim 5 , wherein in a vertical cross-section of the power semiconductor device:
the second load terminal and the second doped semiconductor region laterally overlap with each other; and a transition between the second load terminal and the second doped semiconductor region along the vertical direction is electrically conductive along at least 75% of the total lateral extension of the peripheral volume in the vertical cross-section.

15 . The power semiconductor device of claim 5 , wherein in the peripheral volume, at least one of the first doped semiconductor region and the second doped semiconductor region exhibits a variation-of-lateral-doping (VLD) structure.

16 . The power semiconductor device of claim 5 , wherein the first doped semiconductor region seamlessly joins into a third doped semiconductor region, and wherein the third doped semiconductor region is of a same conductivity type as the first doped semiconductor region and extends along the frontside within the edge termination region.

17 . The power semiconductor device of claim 5 , wherein the negative gradient of the peripheral average dopant dose of the second doped semiconductor region a

Assignees

• Infineon Technologies Ag

Inventors

• Pfaffenlehner Manfred
• Bauer Josef-Georg
• Pfirsch Frank Dieter
• Scheiper Thilo
• Schraml Konrad

Classifications

• H10W10/031

  of isolation regions comprising PN junctions · CPC title

• H10W10/30

  Isolation regions comprising PN junctions · CPC title

• H10D62/129

  Cathode regions of diodes · CPC title

• H10D62/128

  Anode regions of diodes · CPC title

• H10D8/411

  PN diodes having planar bodies · CPC title