Gallium oxide semiconductor structure, vertical gallium oxide-based power device, and preparation method

Patent metadata

Field	Value
Publication number	US-2023127051-A1
Application number	US-202017779573-A
Country	US
Kind code	A1
Filing date	Nov 3, 2020
Priority date	Nov 26, 2019
Publication date	Apr 27, 2023
Grant date	—

Abstract

The present disclosure provides a gallium oxide semiconductor structure, a vertical gallium oxide-based power device, and a preparation method. An unintentionally doped gallium oxide layer (110) is transferred to a highly doped and highly thermally conductive heterogeneous substrate (200) by bonding and thinning; then a heavily doped gallium oxide layer (120) is formed on the gallium oxide layer by treating and ion implantation, thereby preparing the gallium oxide semiconductor structure including the heterogeneous substrate (200), the gallium oxide layer (110), and the heavily doped gallium oxide layer (120) stacked in sequence. In the vertical gallium oxide-based power device prepared on the basis of the gallium oxide semiconductor structure, the gallium oxide layer (110) is a thicker intermediate layer and a carrier concentration of the gallium oxide layer (110) is less than that of the heavily doped gallium oxide layer (120). Therefore, the breakdown voltage of the device is also increased through structural design. The highly thermally conductive heterogeneous substrate (200) improves the heat dissipation performance of the device. The device with multiple Fin structures provides a large amount of current.

First claim

1 . A method for preparing a gallium oxide semiconductor structure, comprising the following steps:
providing a gallium oxide single crystal wafer, wherein a surface of the gallium oxide single crystal wafer is a polished surface; providing a heterogeneous substrate, wherein a surface of the heterogeneous substrate is a polished surface; bonding the polished surface of the gallium oxide single crystal wafer to the polished surface of the heterogeneous substrate; thinning the gallium oxide single crystal wafer to obtain a composite structure comprising the heterogeneous substrate and the gallium oxide layer stacked in sequence; treating a top surface of the gallium oxide layer, wherein the top surface of the gallium oxide layer is facing away from the polished surface of the heterogeneous substrate; and forming a heavily doped gallium oxide layer on the top surface of the gallium oxide layer by performing an ion implantation on the gallium oxide layer, thereby obtaining the gallium oxide semiconductor structure comprising the heterogeneous substrate, the gallium oxide layer, and the heavily doped gallium oxide layer stacked in sequence.

2 . The method for preparing a gallium oxide semiconductor structure according to claim 1 , wherein the heterogeneous substrate comprises one of a silicon carbide substrate, a diamond substrate, an aluminum nitride substrate, and a silicon substrate.

3 . The method for preparing a gallium oxide semiconductor structure according to claim 1 , wherein a carrier concentration of the heterogeneous substrate is greater than 1 × 10 18 /cm 3 .

4 . The method for preparing a gallium oxide semiconductor structure according to claim 1 , wherein a carrier concentration of the gallium oxide layer is lower than that of the heavily doped gallium oxide layer, wherein the carrier concentration of the gallium oxide layer is in a range of 1 × 10 16 /cm 3 to 9 × 10 17 /cm 3 , and the carrier concentration of the heavily doped gallium oxide layer is greater than 1 × 10 19 /cm 3 .

5 . The method for preparing a gallium oxide semiconductor structure according to claim 1 , wherein a method for bonding the polished surface of the gallium oxide single crystal wafer to the polished surface of the heterogeneous substrate comprises surface-activated bonding, and the surface-activated bonding is performed at a vacuum level of 1 × 10 -7 Pa, under a stress of 16 MPa, at a temperature of 25° C.

6 . The method for preparing a gallium oxide semiconductor structure according to claim 1 , wherein a method for thinning the gallium oxide single crystal wafer comprises grinding or wet etching.

7 . The method for preparing a gallium oxide semiconductor structure according to claim 6 , wherein when the grinding is adopted to thin the gallium oxide single crystal wafer, the grinding is performed at a gear speed of 1500 rpm to 3000 rpm, a rotational speed of a workbench of 30 rpm to 120 rpm, a feed speed of 5 µm/min to 30 µm/min, and a grinding time of 30 s to 100 min.

8 . The method for preparing a gallium oxide semiconductor structure according to claim 1 , wherein a method for treating a stop surface of the gallium oxide layer comprises one of chemical mechanical polishing, plasma etching, ion sputtering and chemical etching.

9 . The method for preparing a gallium oxide semiconductor structure according to claim 1 , wherein the ion implantation comprises one of Si ion implantation, Ge ion implantation, Sn ion implantation and Nb ion implantation.

10 . The method for preparing a gallium oxide semiconductor structure according to claim 9 , wherein the Si ion implantation takes place at an energy level of 10 Kev to 80 Kev and at a dose of 1 × 10 15 ions/cm 2 to 5 × 10 16 ions/cm 2 ; the Ge ion implantation takes place at an energy level of 20 Kev to 170 Kev and at a dose of 1 × 10 15 ions/cm 2 to 5 × 10 16 ions/cm 2 ; the Sn ion implantation takes place at an energy level of 30 Kev to 275 Kev and at a dose of 1 × 10 15 ions/cm 2 to 5 × 10 16 ions/cm 2 ; and the Nb ion implantation takes place at an energy level of 25 Kev to 225 Kev and at a dose of 1 × 10 15 ions/cm 2 to 5 × 10 16 ions/cm 2 .

11 . The method for preparing a gallium oxide semiconductor structure according to claim 1 , wherein the depth of the ion implantation is in a range of 10 nm to 60 nm.

12 . The method for preparing a gallium oxide semiconductor structure according to claim 1 , wherein a surface roughness of the polished surface of the gallium oxide single crystal wafer is less than 1 nm, and a surface roughness of the polished surface of the heterogeneous substrate is less than 1 nm.

13 . A gallium oxide semiconductor structure, comprising a heterogeneous substrate, a gallium oxide layer and a heavily doped gallium oxide layer stacked in sequence.

14 . The gallium oxide semiconductor structure according to claim 13 , wherein a carrier concentration of the gallium oxide layer is lower than that of the heavily doped gallium oxide layer, wherein the carrier concentration of the gallium oxide layer is in a range of 1 × 10 16 /cm 3 to 9 × 10 17 /cm 3 , and the carrier concentration of the heavily doped gallium oxide layer is greater than 1 × 10 19 /cm 3 .

15 . The method for preparing a gallium oxide semiconductor structure according to claim 13 , wherein the thickness of the gallium oxide layer is in a range of 5 µm to 100 µm, and the thickness of the heavily doped gallium oxide layer is in a range of 10 nm to 60 nm.

16 . The method for preparing a gallium oxide semiconductor structure according to claim 13 , wherein the heterogeneous substrate comprises one of a silicon carbide substrate, a diamond substrate, an aluminum nitride substrate, and a silicon substrate, and a carrier concentration of the heterogeneous substrate is greater than 1 × 10 18 /cm 3 .

17 . A method for preparing a vertical gallium oxide-based power device, comprising preparing the vertical gallium oxide-based power device by using the method for preparing a gallium oxide semiconductor structure according to claim 1 .

18 . A vertical gallium oxide-based power device, comprising a gallium oxide semiconductor structure according to claim 13 .

Assignees

• Shanghai Inst Microsystem & Information Tech Cas

Inventors

• Ou Xin
• Xu Wenhui
• You Tiangui
• Shen Zhenghao

Classifications

• H10P90/00

  Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement · CPC title

• H10P95/70

  Chemical treatments · CPC title

• H10P52/00

  Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title

• H10P50/20

  Dry etching; Plasma etching; Reactive-ion etching · CPC title

• H10P50/69

  using masks for semiconductor materials · CPC title