Field-effect transistor having fractionally enhanced body structure

Patent metadata

Field	Value
Publication number	US-2023101610-A1
Application number	US-202117490918-A
Country	US
Kind code	A1
Filing date	Sep 30, 2021
Priority date	Sep 30, 2021
Publication date	Mar 30, 2023
Grant date	—

Abstract

An integrated circuit includes an epitaxial layer over a semiconductor substrate. The epitaxial layer has a first conductivity type and a top surface. First, second and third trenches are located in the epitaxial layer. The trenches respectively include first, second and third field plates. First and second body members are located within the epitaxial layer and have a different second conductivity type. The first body member is located between the first and second trenches, and the second body member is located between the second and third trenches. The first body member extends a first distance between the top surface and the substrate, and the second body member extends a lesser second distance between the top surface and the substrate.

First claim

What is claimed is:

1 . An integrated circuit, comprising:
an epitaxial layer over a semiconductor substrate, the epitaxial layer having a first conductivity type and a top surface; first, second and third trenches located in the epitaxial layer, the trenches respectively including first, second and third field plates; first and second body members located within the epitaxial layer and having a different second conductivity type, the first body member located between the first and second trenches and the second body member located between the second and third trenches, the first body member extending a first distance between the top surface and the substrate and the second body member extending a lesser second distance between the top surface and the substrate.

2 . The integrated circuit of claim 1 , further comprising a fourth trench including a fourth field plate and a third body member located between the third and fourth trenches and extending the first distance between the top surface and the substrate.

3 . The integrated circuit of claim 2 , wherein first body member has a lateral width between the first and second trenches and the third body member has the lateral width between the third and fourth trenches, and the first and third body members extend laterally parallel to the first, second, third and fourth trenches by a length that is at least two times the lateral width.

4 . The integrated circuit of claim 2 , wherein the second body member is located directly between the first and third body members, and further comprising a fourth body member located between the second and third trenches and extending the first distance between the top surface and the substrate.

5 . The integrated circuit of claim 1 , wherein the first, second and third field plates each have a top that is a depth below the top surface, the first distance being greater than the depth and the second distance being less than the depth.

6 . The integrated circuit of claim 1 , further comprising third and fourth body members located between the first and second trenches, the third body member extending the first distance between the surface and the substrate and the fourth body member extending the second distance between the surface and the substrate, the fourth body member located between the first and the third body members.

7 . The integrated circuit of claim 1 , further comprising a fourth trench including a fourth field plate, a third body member located between the third and fourth trenches and extending the first distance between the top surface and the substrate, and a fourth body member located between the second and third trenches and extending the first distance between the top surface and the substrate, the fourth body member located directly between the first and the third bodies.

8 . The integrated circuit of claim 1 , further comprising a fourth body member located between the first and second trenches and extending the second distance between the top surface and the substrate, and a fifth body member located between the third and fourth trenches and extending the second distance between the top surface and the substrate, the second body member located directly between the fourth and fifth body members.

9 . The integrated circuit of claim 1 , wherein the first and second body members are connected in parallel to a source region that extends from the top surface to the first and second body members.

10 . The integrated circuit of claim 1 , wherein the first body region is electrically connected to a first body contact having a first width between the first and second trenches and the second body region is electrically connected to a second body contact have a greater second width between the second and third trenches.

11 . The integrated circuit of claim 1 , wherein the first conductivity type is N-type and the second conductivity type is P-type.

12 . A method of forming an integrated circuit, comprising:
forming first, second and third trenches in an epitaxial layer having a first conductivity type over a substrate; forming a polysilicon field plate within each of the trenches; forming a first body region having an opposite second conductivity type between the first and second trenches, the first body region having a first depth below a top surface of the epitaxial layer; and forming a second body region having the second conductivity type between the second and third trenches, the second body region having a greater second depth below the top surface.

13 . The method of claim 12 , further comprising forming a first body contact electrically connected to the first body region and having a first width between the first and second trenches, and forming a second body contact electrically connected to the second body region and having a greater second width between the second and third trenches.

14 . A method of forming an integrated circuit, comprising:
forming first, second and third trenches in an epitaxial layer located over a semiconductor substrate, the epitaxial layer having a first conductivity type and a top surface; forming first, second and third field plates respectively within the first, second and third trenches; forming a first body member within the epitaxial layer between the first and second trenches, the first body member having a different second conductivity type and extending into the epitaxial layer a first distance between the top surface and the substrate; and forming a second body member within the epitaxial layer between the second and third trenches, the second body member having the different second conductivity type and extending into the epitaxial layer a lesser second distance between the top surface and the substrate.

15 . The method of claim 14 , further comprising forming a third body member located between the third trench and a fourth trench, the third body member extending the first distance between the top surface and the substrate.

16 . The method of claim 15 , wherein first body member has a lateral width between the first and second trenches and the third body member has the lateral width between the third and fourth trenches, and the first and third body members extend laterally parallel to the first, second, third and fourth trenches by a length that is at least two times the lateral width.

17 . The method of claim 15 , further comprising forming a fourth body member located between the second and third trenches and extending the first distance between the top surface and the substrate, the second body member located directly between the first and third body members.

18 . The method of claim 14 , wherein the first, second and third field plates each have a top at a depth below the top surface, the first distance being greater than the depth and the second distance being less than the depth.

19 . The method of claim 14 , further comprising forming third and fourth body members located between the first and second trenches, the third body member extending the first distance between the surface and the substrate and the fourth body member extending the second distance between the surface and the substrate, the fourth body member located between the first and the third body members.

20 . The method of claim 14 , further comprising forming a third body member between the third trench and a fourth trench and a fourth body member located between the second and third trenches, the third body member extending the first distance between the top surface and the

Assignees

• Texas Instruments Inc

Inventors

• Lee Meng-Chia
• Kim Sunglyong
• Sridhar Seetharaman
• Pendharkar Sameer

Classifications

• H10D64/2527

  for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies · CPC title

• H10D30/668 Primary

  having trench gate electrodes, e.g. UMOS transistors · CPC title

• H10D30/63

  Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) · CPC title

• H10D30/0297

  using recessing of the gate electrodes, e.g. to form trench gate electrodes · CPC title

• H10D30/0295

  using recessing of the source electrodes · CPC title