Semiconductor devices and manufacturing methods for the same

Patent metadata

Field	Value
Publication number	US-2023096214-A1
Application number	US-202217952637-A
Country	US
Kind code	A1
Filing date	Sep 26, 2022
Priority date	Sep 29, 2021
Publication date	Mar 30, 2023
Grant date	—

Abstract

A semiconductor device includes a plurality of gate electrodes extending on a substrate in a first horizontal direction and each including first and second vertical extension sidewalls that are opposite to each other, a channel arranged on the first vertical extension sidewall of each gate electrode and including a vertical extension portion, a ferroelectric layer and a gate insulating layer that are sequentially located between the channel layer and the first vertical extension sidewall of each gate electrode, an insulating layer on the second vertical extension sidewall of each gate electrode, and a plurality of bit lines electrically connected to the channel layer and extending in a second horizontal direction that is different from the first horizontal direction.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a plurality of gate electrodes extending on a substrate in a first horizontal direction that is parallel to an upper surface of the substrate, wherein each gate electrode of the plurality of gate electrodes includes a first vertical extension sidewall and a second vertical extension sidewall that are opposite to each other; a channel layer on the first vertical extension sidewall of each gate electrode of the plurality of gate electrodes, the channel layer including a vertical extension portion; a ferroelectric layer and a gate insulating layer that are sequentially located between the channel layer and the first vertical extension sidewall of each gate electrode of the plurality of gate electrodes; an insulating layer on the second vertical extension sidewall of each gate electrode of the plurality of gate electrodes; and a plurality of bit lines electrically connected to the channel layer and extending in a second horizontal direction that is different from the first horizontal direction and is parallel to the upper surface of the substrate.

2 . The semiconductor device of claim 1 , wherein each gate electrode of the plurality of gate electrodes comprises:
a main gate portion extending in a vertical direction that is perpendicular to the upper surface of the substrate; and a horizontal extension portion connected to the main gate portion and extending in the second horizontal direction, wherein the main gate portion comprises the first vertical extension sidewall of the gate electrode and the second vertical extension sidewall of the gate electrode.

3 . The semiconductor device of claim 2 , wherein the plurality of gate electrodes each have an L-shaped vertical cross-section.

4 . The semiconductor device of claim 2 , wherein the ferroelectric layer comprises:
a first portion extending, in the vertical direction, on the first vertical extension sidewall of each gate electrode of the plurality of gate electrodes; and a second portion arranged on the horizontal extension portion of each gate electrode of the plurality of gate electrodes.

5 . The semiconductor device of claim 2 , wherein the plurality of gate electrodes comprise:
a first gate electrode and a second gate electrode that are alternately arranged in the second horizontal direction, wherein the first gate electrode and the second gate electrode are mirror-symmetrical with respect to each other.

6 . The semiconductor device of claim 1 , wherein the channel layer comprises:
a main channel layer portion extending in a vertical direction perpendicular to the upper surface of the substrate; and a horizontal extension portion connected to the main channel layer portion and extending in the second horizontal direction.

7 . The semiconductor device of claim 6 , wherein the channel layer has an L-shaped vertical cross-section.

8 . The semiconductor device of claim 6 , wherein the ferroelectric layer comprises:
a first portion extending, in the vertical direction, between the first vertical extension sidewall of each gate electrode of the plurality of gate electrodes and the main channel layer portion of the channel layer; and a second portion between a bottom surface of each gate electrode of the plurality of gate electrodes and the horizontal extension portion of the channel layer.

9 . The semiconductor device of claim 6 , wherein the channel layer comprises: a first channel layer and a second channel layer that are alternately arranged in the second horizontal direction, and
the first channel layer and the second channel layer are mirror-symmetrical with respect to each other.

10 . The semiconductor device of claim 1 , further comprising a floating gate electrode that is between the ferroelectric layer and the gate insulating layer.

11 . The semiconductor device of claim 1 , wherein
the ferroelectric layer comprises a ferroelectric material that has a chemical formula of Hf x M 1−x O y (0<x<1,2≤y≤4, wherein M is at least one of zirconium (Zr), silicon (Si), aluminum (Al), yttrium (Y), gadolinium (Gd), lanthanum (La), scandium (Sc), or strontium (Sr)), and the ferroelectric material has an orthorhombic crystal structure.

12 . The semiconductor device of claim 1 , wherein the channel layer comprises at least one of polysilicon, silicon-germanium, germanium (Ge), InGaZnO x (IGZO), Sn-doped IGZO, W-doped InOx (IWO), InZnO x (IZO), ZnSnO x (ZTO), YZnO x (YZO), copper sulfide (CuS 2 ), copper diselenide (CuSe 2 ), molybdenum disulfide (MoS 2 ), molybdenum diselenide (MoSe 2 ), tungsten diselenide (WSe 2 ), or tungsten disulfide (WS 2 ).

13 . A semiconductor device, comprising:
a plurality of source lines extending on a substrate in a first horizontal direction that is parallel to an upper surface of the substrate; a plurality of bit lines extending in a second horizontal direction at a higher vertical level than the plurality of source lines in a vertical direction that is perpendicular to the upper surface of the substrate; and a plurality of ferroelectric transistors located at separate, respective cross points of the plurality of source lines and the plurality of bit lines, wherein each ferroelectric transistor of the plurality of ferroelectric transistors includes
a gate electrode extending in the first horizontal direction,
a ferroelectric layer on a sidewall of the gate electrode,
a gate insulating layer on a sidewall of the ferroelectric layer, and
a channel layer on a sidewall of the gate insulating layer,
wherein the plurality of ferroelectric transistors include a first ferroelectric transistor and a second ferroelectric transistor, which are adjacent to each other in the second horizontal direction and are mirror-symmetrical with respect to each other.

14 . The semiconductor device of claim 13 , wherein the gate electrode has an L-shaped vertical cross-section.

15 . The semiconductor device of claim 13 , wherein the gate electrode comprises:
a main gate portion extending in the vertical direction; and a horizontal extension portion connected to the main gate portion and extending in the second horizontal direction.

16 . The semiconductor device of claim 15 , wherein the ferroelectric layer is on a sidewall of the main gate portion and an upper surface of the horizontal extension portion.

17 . The semiconductor device of claim 13 , wherein the channel layer has an L-shaped vertical cross-section.

18 . The semiconductor device of claim 13 , wherein the channel layer comprises:
a main channel layer portion extending in the vertical direction; and a horizontal extension portion connected to the main channel layer portion and extending in the second horizontal direction.

19 . The semiconductor device of claim 18 , wherein the ferroelectric layer comprises:
a first portion extending, in the vertical direction, between the sidewall of the gate electrode and the main channel layer portion of the channel layer; and a second portion between a bottom surface of the gate electrode and the horizontal extension portion of the channel layer.

20 . A semiconductor device, comprising:
a plurality of source lines extending on a substrate in a first horizontal direction that is parallel to an upper surface of the substrate; an insulating layer on the plurality of source lines, the insulating layer including a plurality of first sidewalls and a plurality of second sidewalls that oppose separate, respective first sidewalls

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Kyunghwan
• Kim Yongseok
• Kim Hyuncheol
• Park Jongman
• Woo Dongsoo
• Lee Minjun

Classifications

• H10B12/20

  DRAM devices comprising floating-body transistors, e.g. floating-body cells · CPC title

• H10B12/30

  DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells · CPC title

• H10D64/512

  Disposition of the gate electrodes, e.g. buried gates · CPC title

• H10D64/689

  having ferroelectric layers · CPC title

• H10D1/716

  having vertical extensions · CPC title