Trench-gate source follower for low-noise scaled pixel

Patent metadata

Field	Value
Publication number	US-2023094943-A1
Application number	US-202117489735-A
Country	US
Kind code	A1
Filing date	Sep 29, 2021
Priority date	Sep 29, 2021
Publication date	Mar 30, 2023
Grant date	—

Abstract

A trench-gate source-follower (TGSF) transistor is described, such as for integration with image sensor pixels. The TGSF transistor is at least partially built into a trench etched into a substrate. A contiguous doped region is implanted around the inner walls of the trench to form a buried-trench current channel. A trench-gate is formed to have at least a buried portion that fills the volume of the trench. A gate oxide layer can be disposed between the buried portion of the trench-gate and the buried-trench current channel. Drain and source regions are formed on either end of the trench-gate. Activating the trench-gate causes current to flow between the drain and source regions via the buried-trench current channel around the buried portion of the trench-gate. The geometry of the buried-trench current channel can effectively increase the width of the active region of the source-follower transistor without increasing its physical layout width.

First claim

What is claimed is:

1 . A method for manufacturing a trench-gate source-follower (TGSF) transistor block, the method comprising:
forming a buried-trench current channel in a semiconductor substrate, such that the buried-trench current channel is a contiguous doped region implanted into the semiconductor substrate in trench walls that surround a trench etched into the semiconductor substrate; depositing polysilicon to overfill a volume of the trench so that a first portion of the polysilicon conforms to the volume of the trench to form a buried portion of a trench-gate, and a second portion of the polysilicon extends above a surface level of the trench, the surface level being coincident with a surface of the semiconductor substrate; patterning the second portion of the polysilicon to form an exposed portion of the trench-gate; implanting a drain region in the semiconductor substrate adjacent to a first side of the trench-gate; and implanting a source region in the semiconductor substrate adjacent to a second side of the trench-gate opposite the first side.

2 . The method of claim 1 , further comprising:
patterning a gate contact to electrically couple with the trench-gate, a drain contact to electrically couple with the drain region, and a source contact to electrically couple with the source region, such that electrically activating the gate contact activates the buried-trench current channel to provide current flow between the drain contact and the source contact around the buried portion of the trench-gate.

3 . The method of claim 1 , wherein the forming the buried-trench current channel comprises:
etching the trench into the surface of the semiconductor substrate in accordance with a predefined trench geometry to form the trench walls; and implanting one or more doped regions into the trench walls, subsequent to the etching, to form the contiguous doped region, thereby forming the buried-trench current channel.

4 . The method of claim 1 , wherein the forming the buried-trench current channel comprises:
implanting a doped well below the surface of the semiconductor substrate to occupy a volume subsuming both the volume of the trench and the contiguous doped channel region; and etching the trench into the surface of the semiconductor substrate and into the doped well, so that the trench walls formed around the trench define a portion of the doped well as the contiguous doped channel region implanted in the trench walls, thereby forming the buried-trench current channel.

5 . The method of claim 1 , further comprising:
depositing a hard mask on the semiconductor substrate, the hard mask exposing a region of the surface to have a predefined physical trench width and a predefined physical trench length, wherein the trench is etched into the semiconductor substrate via the hard mask so that the trench walls and the surface level accord substantially with the predefined physical trench width, the predefined physical trench length, and a predefined physical trench depth.

6 . The method of claim 1 , further comprising:
growing a gate oxide layer, prior to the depositing the polysilicon, to coat the surface of the semiconductor substrate and to coat the trench walls, such that the volume of the trench as overfilled by the polysilicon is a coated volume accounting for a thickness of the gate oxide layer coating the trench walls.

7 . The method of claim 1 , wherein:
the second portion of the polysilicon extends above the surface level of the trench by an amount exceeding a predefined gate height; and the patterning the second portion comprises polishing the second portion of the polysilicon to form a top surface of the trench-gate substantially at the predefined gate height above the surface level of the trench.

8 . The method of claim 7 , wherein the patterning the second portion further comprises:
depositing a gate mask on the top surface to mask out a region corresponding to a layout width and a layout length of the trench-gate; and etching the second portion of the polysilicon around the gate mask to pattern the exposed portion of the trench-gate.

9 . The method of claim 1 , wherein:
the trench is etched to have a trench length and a trench width; and the patterning the second portion of the polysilicon forms the exposed portion of the trench-gate to have a gate layout length that coincides with the trench length and a gate layout width that exceeds the trench width.

10 . The method of claim 1 , wherein:
implanting the drain region comprises implanting a first lighter-doped region to electrically couple with a portion of the buried-trench current channel at the first side of the trench-gate, and implanting a first higher-doped region within the first lighter-doped region; and implanting the source region comprises implanting a second lighter-doped region to electrically couple with a portion of the buried-trench current channel at the second side of the trench-gate, and implanting a second higher-doped region within the second lighter-doped region.

11 . A trench-gate source-follower (TGSF) transistor block comprising:
a buried-trench current channel formed in a semiconductor substrate as a contiguous doped region implanted into the semiconductor substrate in trench walls that surround a trench etched into the semiconductor substrate; a trench-gate formed by depositing polysilicon to overfill a volume of the trench so that the trench-gate comprises:
a buried portion formed by a first portion of the polysilicon filling and conforming to the volume of the trench; and
an exposed portion formed by patterning a second portion of the polysilicon that extends above a surface level of the trench, the surface level being coincident with a surface of the semiconductor substrate;
a drain region implanted in the semiconductor substrate adjacent to a first side of the trench-gate; and a source region implanted in the semiconductor substrate adjacent to a second side of the trench-gate opposite the first side.

12 . The TGSF transistor block of claim 11 , further comprising:
a gate contact patterned on the semiconductor substrate to electrically couple with the trench-gate; a drain contact patterned on the semiconductor substrate to electrically couple with the drain region; and a source contact patterned on the semiconductor substrate to electrically couple with the source region, such that electrically activating the gate contact activates the buried-trench current channel to provide current flow between the drain contact and the source contact around the buried portion of the trench-gate.

13 . The TGSF transistor block of claim 11 , wherein the buried-trench current channel is formed in the semiconductor substrate by:
etching the trench into the surface of the semiconductor substrate in accordance with a predefined trench geometry to form the trench walls; and implanting one or more doped regions into the trench walls, subsequent to the etching, to form the contiguous doped region, thereby forming the buried-trench current channel.

14 . The TGSF transistor block of claim 11 , wherein the buried-trench current channel is formed in the semiconductor substrate by:
implanting a doped well below the surface of the semiconductor substrate to occupy a volume subsuming both the volume of the trench and the contiguous doped channel region; and etching the trench into the surface of the semiconductor substrate and into the doped well, so that the trench walls formed around the trench define a portion of the doped well as the contiguous doped region implanted in the trench walls, thereby

Assignees

• Shenzhen Goodix Tech Co Ltd

Inventors

• Gao Yunfei
• Oh Tae Seok
• Xiao Jinwen

Classifications

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D64/512

  Disposition of the gate electrodes, e.g. buried gates · CPC title

• H10D64/027

  by etching at gate locations · CPC title

• H10D30/668

  having trench gate electrodes, e.g. UMOS transistors · CPC title

• H10D30/0275

  forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions · CPC title