Semiconductor device

Patent metadata

Field	Value
Publication number	US-2023074352-A1
Application number	US-202217874603-A
Country	US
Kind code	A1
Filing date	Jul 27, 2022
Priority date	Sep 7, 2021
Publication date	Mar 9, 2023
Grant date	—

Abstract

Provide is a highly reliable semiconductor device in which stress generated in a semiconductor chip is reduced and an increase in thermal resistance is suppressed. The semiconductor device includes: a semiconductor chip including a first main electrode on one surface thereof and a second main electrode and a gate electrode on the other surface thereof; a first electrode connected to the one surface of the semiconductor chip via a first bonding material; and a second electrode connected to the other surface of the semiconductor chip via a second bonding material. The first electrode is a plate-shaped electrode and has a groove in a region overlapping with the semiconductor chip. The groove penetrates in a thickness direction of the first electrode and reaches an end portion of the first electrode when viewed in a plan view.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a semiconductor chip including
a first main electrode on one surface thereof, and
a second main electrode and a gate electrode on another surface thereof;
a first electrode connected to the one surface of the semiconductor chip via a first bonding material; and a second electrode connected to the other surface of the semiconductor chip via a second bonding material, wherein the first electrode is a plate-shaped electrode and has a groove in a region overlapping with the semiconductor chip, and the groove penetrates in a thickness direction of the first electrode and has a shape that reaches an end portion of the first electrode when viewed in a plan view.

2 . The semiconductor device according to claim 1 , wherein
the groove has a width larger than a thickness of the first bonding material.

3 . The semiconductor device according to claim 1 , wherein
the groove is provided at a position overlapping with the second electrode.

4 . The semiconductor device according to claim 1 , wherein
a distance from an end portion of a connection surface of the second electrode with the semiconductor chip to an end portion of the semiconductor chip is set to W, a distance from the end portion of the connection surface of the second electrode with the semiconductor chip to a center line of the groove is set to J, and when J/W is defined as X, a position of the center line of the groove satisfies the following Equation (1).
−1.2< X< 0.3   (1)

5 . The semiconductor device according to claim 1 , wherein
the first bonding material and the second bonding material are solders containing Sn as a main component.

6 . The semiconductor device according to claim 1 , wherein
an end portion of the second electrode is located inside an end portion of the semiconductor chip, and the end portion of the first electrode is located outside the end portion of the semiconductor chip.

7 . The semiconductor device according to claim 1 , wherein
an end portion of the second electrode is located inside an end portion of the semiconductor chip, and the end portion of the first electrode is located inside the end portion of the semiconductor chip.

8 . The semiconductor device according to claim 1 , wherein
the groove includes a branched groove provided so as to communicate with the groove and branched from the groove.

Assignees

• Hitachi Power Semiconductor Device Ltd

Inventors

• Takeda Naoki
• Tanie Hisashi
• Ashida Kisho
• Harubeppu Yu
• Onda Tomohiro
• Nakamura Masato

Classifications

• H10W72/551

  Materials of bond wires · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/07353

  changes in shapes · CPC title