Method of forming interconnect for semiconductor device

Patent metadata

Field	Value
Publication number	US-2023045689-A1
Application number	US-202217968201-A
Country	US
Kind code	A1
Filing date	Oct 18, 2022
Priority date	Oct 24, 2019
Publication date	Feb 9, 2023
Grant date	—

Abstract

A method of forming an interconnect structure for semiconductor devices is described. The method comprises etching a patterned interconnect stack for form first conductive lines and expose a top surface of a first etch stop layer; etching the first etch stop layer to form second conductive lines and expose a top surface of a barrier layer; and forming a self-aligned via.

First claim

What is claimed is:

1 . A method of forming an interconnect structure, the method comprising:
etching a lithographic patterning structure to form a partially patterned structure having first conductive lines and to expose a top surface of a first etch stop layer; etching the first etch stop layer of the partially patterned structure to form second conductive lines and expose a top surface of a barrier layer; and forming a self-aligned via.

2 . The method of claim 1 , wherein the lithographic patterning structure comprises a substrate having the barrier layer thereon, a first metal layer on the barrier layer, the first etch stop layer on the first metal layer, a second metal layer on the first etch stop layer, a second etch stop layer on the second metal layer, a hard mask layer on the second etch stop layer, a first dielectric layer on the hard mask layer, and a patterned photoresist on the first dielectric layer.

3 . The method of claim 2 , wherein the first dielectric layer comprises one or more of a bottom anti-reflective coating (BARC) or a spin-on dielectric material.

4 . The method of claim 2 , wherein etching the lithographic patterning structure comprises etching the second metal layer in a first direction to the top surface of the first etch stop layer.

5 . The method of claim 4 , wherein forming the first conductive lines comprises exposing the lithographic patterning structure to an etch gas and etching the lithographic patterning structure with an etch rate in a range of about 0.5 nm/s to about 5 nm/s.

6 . The method of claim 5 , wherein forming the second conductive lines comprises sputtering a sputtered hard mask on at least one sidewall of the first conductive lines during etching of the first metal layer.

7 . The method of claim 6 , wherein sputtering the sputtered hard mask comprises adding a dilution gas to the etch gas.

8 . The method of claim 7 , wherein the sputtered hard mask comprises one or more of silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), aluminum oxide (AlOx), or aluminum nitride (AlN), the second conductive lines comprise ruthenium (Ru), and the dilution gas comprises nitrogen (N2).

9 . The method of claim 2 , wherein the first metal layer and the second metal layer independently comprise one or more of tungsten (W), cobalt (Co), ruthenium (Ru), molybdenum (Mo), aluminum (Al), copper (Cu), silicide, or graphene.

10 . The method of claim 2 , wherein the first etch stop layer and the second etch stop layer independently comprise one or more of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), tungsten (W), cobalt (Co), ruthenium (Ru), niobium (Nb), or niobium nitride (NbN).

11 . The method of claim 2 , wherein the hard mask layer comprises one or more of silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), aluminum oxide (AlOx), or aluminum nitride (AlN).

12 . The method of claim 11 , wherein the hard mask layer comprises silicon oxide (SiO) and the second metal comprises one or more of tungsten (W), cobalt (Co), molybdenum (Mo), aluminum (Al), copper (Cu), silicide, or graphene.

13 . The method of claim 1 , wherein forming the self-aligned via comprises:
depositing a second dielectric material on the first conductive lines and second conductive lines; etching the second dielectric material to expose an upper surface of the first conductive lines; etching the second dielectric material to expose an upper surface of the first etch stop layer; and removing the second dielectric material.

14 . The method of claim 13 , wherein the second dielectric material comprises one or more of a bottom anti-reflective coating (BARC) or a spin-on dielectric material.

15 . The method of claim 1 , wherein the barrier layer is a metal liner.

16 . The method of claim 15 , wherein the metal liner comprises one or more of tantalum (Ta), titanium (Ti), tantalum nitride (TaN), titanium nitride (TiN), or tantalum/tantalum nitride (Ta/TaN).

17 . A method of forming an interconnect structure, the method comprising:
etching a lithographic patterning structure to form a partially patterned structure, the lithographic patterning structure comprising a substrate having a barrier layer thereon, a ruthenium layer on the barrier layer, a titanium nitride (TiN) layer on the ruthenium layer, a metal layer comprising one or more of tungsten (W), cobalt (Co), molybdenum (Mo), aluminum (Al), copper (Cu), silicide, or graphene on the titanium nitride (TiN) layer, a first etch stop layer on the metal layer, a silicon oxide layer on the first etch stop layer, a spin-on dielectric material on the silicon oxide layer, and a patterned photoresist on the spin-on dielectric material; etching the partially patterned structure to form first conductive lines and expose a top surface of the titanium nitride (TiN) layer; etching the titanium nitride (TiN) layer to form second conductive lines and expose a top surface of the barrier layer; and forming a self-aligned via.

18 . The method of claim 17 , wherein the barrier layer comprises one or more of tantalum (Ta), titanium (Ti), tantalum nitride (TaN), titanium nitride (TiN), or tantalum/tantalum nitride (Ta/TaN).

19 . The method of claim 17 , further comprising:
forming a second lithographic patterning structure over a top surface of the first conductive lines and second conductive lines, the second lithographic patterning structure comprising a dielectric layer and a photoresist on the dielectric layer; etching the second lithographic patterning structure to remove the photoresist and expose an upper surface of the first conductive lines to form a second partially patterned structure comprising the dielectric layer, wherein the dielectric layer is etched to the upper surface of the first conductive lines; etching the second partially patterned structure to expose an upper surface of the first etch stop layer; and removing the second partially patterned structure to form the self-aligned via.

20 . The method of claim 19 , further comprising etching the first etch stop layer and the barrier layer.

Assignees

• Applied Materials Inc

Inventors

• Jiang Hao
• Lu Chi
• Ren He
• Lang Chi-I
• Hwang Ho-Yung David
• Naik Mehul

Classifications

• H10W20/0633

  using subtractive patterning of the conductive members · CPC title

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10P76/2043

  using an anti-reflective coating · CPC title

• H10P50/266

  by vapour etching only · CPC title

• H10P50/246

  of Group III-V materials · CPC title