Semiconductor processing tool and method for passivation layer formation and removal

Patent metadata

Field	Value
Publication number	US-2023042277-A1
Application number	US-202217653780-A
Country	US
Kind code	A1
Filing date	Mar 7, 2022
Priority date	Aug 6, 2021
Publication date	Feb 9, 2023
Grant date	—

Abstract

A semiconductor processing tool performs passivation layer deposition and removal in situ. A transport mechanism included in the semiconductor processing tool transfers a semiconductor structure through different deposition chambers (e.g., without breaking or removing a vacuum environment). Accordingly, the semiconductor processing tool deposits a target layer that is thinner on, or even absent from, a metal layer, such that contact resistance is reduced between a conductive structure formed over the target layer and the metal layer. As a result, electrical performance of a device including the conductive structure is improved. Moreover, because the process is performed in situ (e.g., without breaking or removing the vacuum) in the semiconductor processing tool, production time and risk of impurities in the conductive structure are reduced. As a result, throughput is increased, and chances of spoiled wafers are decreased.

First claim

What is claimed is:

1 . A system, comprising:
a first chamber configured to perform a cleaning process on a wafer; a second chamber configured to deposit a passivation layer on the wafer; a third chamber configured to deposit a target layer on the wafer; a fourth chamber configured to etch the passivation layer from the wafer; a transport mechanism configured to move the wafer between the first chamber, the second chamber, the third chamber, and the fourth chamber; and a mainframe enclosing the first chamber, the second chamber, the third chamber, the fourth chamber, and the transport mechanism and configured to maintain a vacuum environment during movement of the wafer between the first chamber, the second chamber, the third chamber, and the fourth chamber.

2 . The system of claim 1 , further comprising:
at least one pump configured to provide an air curtain between the mainframe and one or more of the first chamber, the second chamber, the third chamber, or the fourth chamber.

3 . The system of claim 2 , wherein the at least one pump and the mainframe are configured to maintain the vacuum environment at least at 10 -7 torr.

4 . The system of claim 1 , wherein the transport mechanism comprises one or more robotic arms configured to grasp, move, and release the wafer.

5 . The system of claim 1 , wherein the first chamber, the second chamber, the third chamber, and the fourth chamber configured to maintain a vacuum at least at 10 -10 torr.

6 . The system of claim 1 , wherein the first chamber, the fourth chamber, or a combination thereof include a nozzle configured to inject gas.

7 . The system of claim 1 , wherein the first chamber includes a nozzle configured to inject gas.

8 . The system of claim 1 , wherein the first chamber, the fourth chamber, or a combination thereof include a remote plasma system configured to inject plasma.

9 . The system of claim 1 , wherein the first chamber, the fourth chamber, or a combination thereof receive plasma from a direct plasma system configured to generate plasma.

10 . The system of claim 1 , wherein the second chamber, the third chamber, or a combination thereof receive precursor materials from an ampoule storage system and a nozzle configured to inject the precursor materials.

11 . A method, comprising:
providing a wafer into a mainframe of a system, wherein the mainframe is configured to maintain a vacuum environment; performing a cleaning process on the wafer in a first chamber of the system; moving the wafer to a second chamber of the system in the mainframe under vacuum ; forming a passivation layer on the wafer in the second chamber; moving the wafer to a third chamber of the system in the mainframe under vacuum; forming a target layer on the wafer in the third chamber; moving the wafer to a fourth chamber of the system in the mainframe under vacuum ; and etching the passivation layer from the wafer in the fourth chamber.

12 . The method of claim 11 , wherein the cleaning process uses a hydrogen gas, argon gas, helium gas, hydrogen plasma, argon plasma, helium plasma, or a combination thereof.

13 . The method of claim 11 , wherein the target layer comprises a nitride, a metal, or a combination thereof.

14 . The method of claim 11 , wherein the passivation layer comprises a nitrogen-based head-group, a sulfur-based head-group, a phosphorus-based head-group, a triazole derivative, a thiol, or a thiol derivative.

15 . The method of claim 11 , wherein the passivation layer comprises an alkyne of the form RC=CR' or an alkene of the RC=CR', wherein R is H x or C x H y .

16 . A method, comprising:
cleaning a wafer having a metal layer, at least one etch stop layer (ESL), and a dielectric layer, wherein the dielectric layer includes a recessed portion such that the metal layer is at least partially exposed; forming a passivation layer on an exposed portion of the metal layer, wherein the passivation layer is formed without disturbing a vacuum environment surrounding the wafer; forming a target layer on sidewalls of the recessed portion, wherein the passivation layer prevents formation of the target layer on a bottom surface of the recessed portion, wherein the target layer is formed without disturbing the vacuum environment surrounding the wafer; and etching the passivation layer from the wafer, wherein the passivation layer is etched without disturbing the vacuum environment surrounding the wafer.

17 . The method of claim 16 , further comprising:
scanning the wafer to determine one or more parameters associated with cleaning the wafer, forming the passivation layer, forming the target layer, or etching the passivation layer.

18 . The method of claim 16 , wherein etching the passivation layer includes plasma striking, thermal annealing, or a combination thereof.

19 . The method of claim 16 , wherein cleaning the wafer reduces metal oxide at the exposed portion of the metal layer.

20 . The method of claim 16 , wherein the passivation layer comprises a dry self-assembling monolayer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Kuo Chia-Pang
• Liu Yao-Min
• Chin Shu-Cheng
• Chi Chih-Chien
• Weng Cheng-Hui

Classifications

• H10P72/3304

  characterised by movements or sequence of movements of transfer devices · CPC title

• H10W20/0765

  the thin functional dielectric layers being temporary, e.g. sacrificial layers · CPC title

• H10W20/034

  bottomless barrier, adhesion or liner layers · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10P50/244 Primary

  comprising alternated and repeated etching and passivation steps · CPC title