Electronic package and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-2023039430-A1
Application number	US-202117395215-A
Country	US
Kind code	A1
Filing date	Aug 5, 2021
Priority date	Aug 5, 2021
Publication date	Feb 9, 2023
Grant date	—

Abstract

An electronic package includes a patterned conductive layer and at least one conductive protrusion on the patterned conductive layer. The at least one conductive protrusion has a first top surface. The patterned conductive layer and the at least one conductive protrusion define a space. The electronic package further includes a first electronic component disposed in the space and a plurality of conductive pillars on the first electronic component. The conductive pillars have a second top surface. The first top surface is substantially level with the second top surface.

First claim

What is claimed is:

1 . An electronic package, comprising:
a patterned conductive layer; at least one conductive protrusion on the patterned conductive layer, the at least one conductive protrusion having a first top surface, wherein the patterned conductive layer and the at least one conductive protrusion define a space; a first electronic component disposed in the space; and a plurality of conductive pillars on the first electronic component, the conductive pillars having a second top surface, wherein the first top surface is substantially level with the second top surface.

2 . The electronic package of claim 1 , wherein the patterned conductive layer and the at least one conductive protrusion are metallographically distinct.

3 . The electronic package of claim 1 , wherein the patterned conductive layer comprises a leadframe including a die paddle region and a lead region around the die paddle region, the at least one conductive protrusion is disposed on the die paddle region and/or the lead region, the die paddle region has a first surface in contact with the at least one conductive protrusion and a second surface opposite to the first surface, and a roughness of the first surface of the die paddle region is substantially the same as a roughness of the second surface of the die paddle region.

4 . The electronic package of claim 1 , further comprising a second electronic component stacked on the first electronic component and aside the second conductive pillar.

5 . The electronic package of claim 4 , further comprising a conductive structure between the first electronic component and the second electronic component, wherein the conductive structure electrically connects the second electronic component to the first electronic component.

6 . The electronic package of claim 1 , further comprising a first conductive via on the at least one conductive protrusion and a second conductive via on the conductive pillar, wherein a depth of the first conductive via is substantially the same as a depth of the second conductive via.

7 . The electronic package of claim 3 , wherein the first electronic component has a first backside surface attached to the die paddle region of the leadframe, and the at least one conductive protrusion is electrically connected to the first backside surface of the first electronic component.

8 . An electronic package, comprising:
a patterned conductive layer; at least one conductive protrusion on the patterned conductive layer, wherein the patterned conductive layer and the at least one conductive protrusion define a space; a first electronic component disposed in the space; a second electronic component stacked on the first electronic component and uncovering a portion of the first electronic component; a plurality of conductive pillars on the portion of the first electronic component; and a dielectric layer embedding the first electronic component and the second electronic component.

9 . The electronic package of claim 8 , wherein the second electronic component is electrically connected to the first electronic component.

10 . The electronic package of claim 8 , further comprising a second conductive pillar on the second electronic component, wherein the conductive pillar has a second lower surface in contact with the first electronic component and a second upper surface opposite to the second lower surface; the second conductive pillar has a third lower surface in contact with the second electronic component and a third upper surface opposite to the third lower surface; and the second upper surface is substantially level with the third upper surface.

11 . The electronic package of claim 8 , further comprising a first conductive via on the at least one conductive protrusion and a second conductive via on the conductive pillar.

12 . The electronic package of claim 11 , wherein a depth of the first conductive via is substantially the same as a depth of the second conductive via.

13 . The electronic package of claim 8 , wherein the patterned conductive layer comprises a leadframe having a first surface and a second surface opposite to the first surface, and the at least one conductive protrusion and the first electronic component are disposed on the first surface of the leadframe; and wherein the electronic package further comprises a third electronic component on the second surface of the leadframe or on the first surface of the leadframe.

14 . The electronic package of claim 8 , wherein the patterned conductive layer comprises a leadframe having a first surface and a second surface opposite to the first surface, and the at least one conductive protrusion and the first electronic component are disposed on the first surface of the leadframe; and wherein the electronic package further comprises a heat sink on the first surface or the second surface of the leadframe.

15 . The electronic package of claim 8 , further comprising a first attachment layer between the first electronic component and the patterned conductive layer, wherein the first attachment layer is electrically conductive.

16 . The electronic package of claim 8 , further comprising a circuit layer on the dielectric layer, wherein the circuit layer is electrically connected to the at least one conductive protrusion and/or the conductive pillars.

17 . The electronic package of claim 16 , further comprising an electronic device on the circuit layer, wherein the electronic device is electrically connected to the circuit layer.

18 . A method for manufacturing an electronic package, comprising:
providing a patterned conductive layer; forming a plurality of conductive protrusions on the patterned conductive layer by an additive process to define a space on the patterned conductive layer; disposing an electronic component in the space on the patterned conductive layer; and forming a conductive pillar on the electronic component.

19 . The method of claim 18 , further comprising forming a dielectric layer to encapsulate the patterned conductive layer, the plurality of conductive protrusions, the electronic component and the conductive pillar.

20 . The method of claim 19 , further comprising removing a portion of the dielectric layer to expose the plurality of conductive protrusions and the conductive pillar.

Assignees

• Advanced Semiconductor Eng

Inventors

• Yen You-Lung
• Appelt Bernd Karl
• Essig Kay Stefan

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/823

  Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W74/111

  the semiconductor body being completely enclosed · CPC title

• H10W70/465

  Bumps or wires · CPC title