Power architecture for non-volatile memory

Patent metadata

Field	Value
Publication number	US-2023017388-A1
Application number	US-202217873850-A
Country	US
Kind code	A1
Filing date	Jul 26, 2022
Priority date	Feb 5, 2021
Publication date	Jan 19, 2023
Grant date	—

Abstract

Methods, systems, and devices for power architecture for non-volatile memory are described. A memory device may be configured to operate in a first mode and a second mode (e.g., a low power mode). When operating in the first mode, a voltage may be supplied from a power source (e.g., a power management integrated circuit) to a memory array and one or more associated components via a regulator. When the memory device transitions to operate in the second mode, some of the components supplied from the power source may be powered by a charge pump. Control information associated with the memory array may be stored to the one or more components (e.g., to a cache) that are powered by a charge pump.

First claim

1 . (canceled)

2 . An apparatus, comprising:
a non-volatile memory array configured to operate in a first mode associated with a first power state of the apparatus and a second mode associated with a second power state of the apparatus; a regulator configured to receive a first voltage and supply a second voltage to one or more components associated with the non-volatile memory array based at least in part on operating in the first mode and to isolate the one or more components from a first voltage source based at least in part on operating in the second mode; a second voltage source configured to supply a third voltage to one or more input/output (I/O) components associated with the non-volatile memory array based at least in part on operating in the first mode or the second mode; and a charge pump configured to receive the third voltage and supply the second voltage to the one or more components associated with the non-volatile memory array based at least in part on operating in the second mode.

3 . The apparatus of claim 2 , wherein the one or more components associated with the non-volatile memory array comprise:
a cache configured to store control information and user data when the non-volatile memory array is operating in the second mode.

4 . The apparatus of claim 3 , wherein the non-volatile memory array is configured to operate using the control information stored in the cache when operating in the first mode, and wherein the user data is configured to be stored to the non-volatile memory array when the non-volatile memory array is operating in the first mode.

5 . The apparatus of claim 3 , wherein the charge pump is configured to power the cache when the non-volatile memory array is operating in the second mode.

6 . The apparatus of claim 2 , further comprising:
a controller configured to cause the apparatus to apply a signal to the regulator based at least in part on operating in the first mode, wherein the regulator is configured to couple the one or more components associated with the non-volatile memory array with the first voltage source based at least in part on the controller applying the signal.

7 . The apparatus of claim 6 , wherein the controller is configured to cause the apparatus to:
remove the signal from the regulator based at least in part on operating in the second mode, wherein the regulator is configured to isolate the one or more components associated with the non-volatile memory array from the first voltage source based at least in part on the controller removing the signal; and activate the charge pump based at least in part on removing the signal from the regulator.

8 . The apparatus of claim 2 , wherein the charge pump is configured to be activated based at least in part on the non-volatile memory array operating in the second mode.

9 . The apparatus of claim 2 , wherein the regulator is configured as a diode based at least in part on the non-volatile memory array operating in the second mode.

10 . The apparatus of claim 2 , wherein the regulator comprises at least one transistor configured to couple the one or more components associated with the non-volatile memory array with the first voltage source based at least in part on operating in the first mode and isolate the one or more components from the first voltage source based at least in part on operating in the second mode.

11 . A non-transitory computer-readable medium storing code comprising instructions which, when executed by a processor of an electronic device, cause the electronic device to:
supply, by a regulator, a first voltage to a non-volatile memory array and one or more components associated with the non-volatile memory array based at least in part on operating in a first mode; receive, at a charge pump, a second voltage from a voltage source that is configured to supply the second voltage to one or more input/output (I/O) components associated with the non-volatile memory array; deactivate the regulator to cease supplying the first voltage to the non-volatile memory array and the one or more components based at least in part on operating the non-volatile memory array in a second mode; and supply, by the charge pump, the first voltage to the one or more components based at least in part on operating the non-volatile memory array in the second mode.

12 . The non-transitory computer-readable medium of claim 11 , wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to:
determine to operate the non-volatile memory array in the second mode, wherein the regulator is deactivated based at least in part on determining to operate the non-volatile memory array in the second mode.

13 . The non-transitory computer-readable medium of claim 12 , wherein the one or more components associated with the non-volatile memory array comprises a cache, and wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to:
write data from the non-volatile memory array to the cache based at least in part on determining to operate the non-volatile memory array in the second mode, wherein the cache is configured to be powered based at least in part on the non-volatile memory array operating in the second mode.

14 . The non-transitory computer-readable medium of claim 12 , wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to:
deactivate the regulator by removing a signal from the regulator based at least in part on determining to operate the non-volatile memory array in the second mode, wherein the non-volatile memory array is isolated from a first voltage source based at least in part on removing the signal from the regulator.

15 . The non-transitory computer-readable medium of claim 14 , wherein the signal is removed from the regulator during a duration associated with supplying the first voltage to the one or more components.

16 . The non-transitory computer-readable medium of claim 12 , wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to:
supply the first voltage to the one or more components by applying a signal to the charge pump based at least in part on determining to operate the non-volatile memory array in the second mode, wherein the charge pump is configured to apply the first voltage to the one or more components based at least in part on receiving the second voltage from the voltage source.

17 . The non-transitory computer-readable medium of claim 11 , wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to determine to:
operate the non-volatile memory array in the first mode, wherein the regulator is activated based at least in part on determining to operate the non-volatile memory array in the first mode.

18 . The non-transitory computer-readable medium of claim 17 , wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to:
activate the regulator based at least in part on determining to operate the non-volatile memory array in the first mode, wherein the first voltage is applied to the non-volatile memory array based at least in part on activating the regulator; and deactivate the charge pump to cease supplying the first voltage to the one or more components based at least in part on activating the regulator.

19 . The non-tran

Assignees

• Micron Technology Inc

Inventors

• Lin Qisong
• Xu Shuai
• Parry Jonathan S
• Binfet Jeremy
• Piccardi Micheie
• Liang Qing

Classifications

• G06F2212/1024

  Latency reduction · CPC title

• G11C16/30 Primary

  Power supply circuits · CPC title

• G06F2212/7208

  Multiple device management, e.g. distributing data over multiple flash devices · CPC title

• G06F2212/7203

  Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks · CPC title

• G06F3/0634

  by changing the state or mode of one or more devices · CPC title