System memory-aware circuit region partitioning

Patent metadata

Field	Value
Publication number	US-2023008569-A1
Application number	US-202117369329-A
Country	US
Kind code	A1
Filing date	Jul 7, 2021
Priority date	Jul 7, 2021
Publication date	Jan 12, 2023
Grant date	—

Abstract

To increase the efficiency of an electronic design automation (EDA) process, for a putative integrated circuit design for which computerized routing is to be carried out within an EDA program, run a sweep line algorithm selectively on active metal shapes in said putative design for different layers, to determine a total number of said active metal shapes, and compute a memory requirement for computerized routing on said active shapes based on said total number of said active shapes. For said putative design, compute a memory requirement for computerized routing on inactive metal shapes based on a total number of said inactive shapes; partition said putative design into a plurality of partitions, based on said memory requirement for computerized routing on said active and inactive shapes, such that an available system memory is not exceeded. Separately run a routing job on each of said plurality of partitions.

First claim

What is claimed is:

1 . A method for increasing the efficiency of an electronic design automation process, the method comprising:
for a putative integrated circuit design for which computerized routing is to be carried out within an electronic design analysis program, running a sweep line algorithm selectively on active metal shapes in said putative design for different layers of said putative design, to determine a total number of said active metal shapes, and computing a memory requirement for computerized routing on said active metal shapes based on said total number of said active metal shapes; for said putative integrated circuit design, computing a memory requirement for computerized routing on inactive metal shapes based on a total number of said inactive metal shapes; partitioning said putative integrated circuit design into a plurality of partitions, based on said memory requirement for computerized routing on said active metal shapes and said memory requirement for computerized routing on said inactive metal shapes, such that an available system memory is not exceeded; and separately running a routing job on each of said plurality of partitions.

2 . The method of claim 1 , wherein computing said memory requirement for computerized routing on said inactive metal shapes is carried out without running a sweep line algorithm on said inactive metal shapes.

3 . The method of claim 2 , further comprising computing said available system memory on-the-fly.

4 . The method of claim 3 , wherein computing said memory requirement for said computerized routing on said active metal shapes and computing said memory requirement for said computerized routing on said inactive metal shapes comprises applying a formula:
M=n 1 x+n 2 x n
wherein M is a total memory requirement for said computerized routing on said active metal shapes and said computerized routing on said inactive metal shapes, n 1 is a count of said active shapes, n 2 is a count of said inactive shapes, n is a polynomial exponent deduced empirically, and x is a minimum memory taken by a node and its dependent data structure.

5 . The method of claim 4 , wherein said partitioning of said putative integrated circuit design into said plurality of partitions comprises dividing said total memory requirement M by said available system memory and rounding to a next highest integer.

6 . The method of claim 3 , wherein said routing job enforces end-of-line design rules in extreme ultraviolet (EUV) technology.

7 . The method of claim 1 , wherein said partitioning step, said step of running said routing job, said step of computing said memory requirement for computerized routing on said active metal shapes, and said step of computing said memory requirement for computerized routing on said inactive metal shapes, are carried out at a routing stage and not at a placement stage of said electronic design automation process.

8 . The method of claim 1 , wherein said putative integrated circuit design comprises a two-dimensional design.

9 . The method of claim 1 , wherein said step of separately running said routing job on each of said plurality of partitions is carried out sequentially.

10 . The method of claim 1 , wherein said step of separately running said routing job on each of said plurality of partitions.is carried out at least in part by multithreading.

11 . The method of claim 1 , further comprising updating said putative integrated circuit design based on said routing on each of said plurality of partitions.

12 . The method of claim 11 , further comprising fabricating a physical integrated circuit in accordance with said updated putative circuit design.

13 . The method of claim 12 , further comprising:
rendering said updated putative circuit design in a design language; preparing a layout based on said updated putative circuit design rendered in said design language; and instantiating said layout as a design structure; wherein said physical integrated circuit is fabricated in accordance with said design structure.

15 . A computer comprising:
a memory; and at least one processor, coupled to said memory, and operative to increase the efficiency of an electronic design automation process by:
for a putative integrated circuit design for which computerized routing is to be carried out within an electronic design analysis program, running a sweep line algorithm selectively on active metal shapes in said putative design for different layers of said putative design, to determine a total number of said active metal shapes, and computing a memory requirement for computerized routing on said active metal shapes based on said total number of said active metal shapes;
for said putative integrated circuit design, computing a memory requirement for computerized routing on inactive metal shapes based on a total number of said inactive metal shapes;
partitioning said putative integrated circuit design into a plurality of partitions, based on said memory requirement for computerized routing on said active metal shapes and said memory requirement for computerized routing on said inactive metal shapes, such that an available system memory is not exceeded; and
separately running a routing job on each of said plurality of partitions.

16 . The computer of claim 15 , wherein said at least one processor computes said memory requirement for computerized routing on said inactive metal shapes without running a sweep line algorithm on said inactive metal shapes.

17 . The computer of claim 16 , wherein said at least one processor is further operative to compute said available system memory on-the-fly.

18 . The computer of claim 17 , wherein computing said memory requirement for said computerized routing on said active metal shapes and computing said memory requirement for said computerized routing on said inactive metal shapes comprises applying a formula:
M=n 1 x+n 2 x n
wherein M is a total memory requirement for said computerized routing on said active metal shapes and said computerized routing on said inactive metal shapes, n 1 is a count of said active shapes, n 2 is a count of said inactive shapes, n is a polynomial exponent deduced empirically, and x is a minimum memory taken by a node and its dependent data structure; and
wherein said partitioning of said putative integrated circuit design into said plurality of partitions comprises dividing said total memory requirement M by said available system memory and rounding to a next highest integer.

19 . The computer of claim 15 , wherein said at least one processor is further operative to increase the efficiency of the electronic design automation process by:
updating said putative integrated circuit design based on said routing on each of said plurality of partitions; render said updated putative circuit design in a design language; prepare a layout based on said updated putative circuit design rendered in said design language; instantiate said layout as a design structure; and provide said design structure to fabrication equipment to facilitate fabrication of a physical integrated circuit in accordance with said design structure.

20 . A non-transitory computer readable medium comprising computer executable instructions which when executed by a computer performing an electronic design automation process cause the computer to perform a method which increases the efficiency of the electronic design automation process, the method comprising:
for a putative i

Assignees

• IBM

Inventors

• Pandey Diwesh

Classifications

• G06F30/394 Primary

  Routing (G06F30/396 takes precedence) · CPC title

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title