Capacitance extraction method for semiconductor sadp metal wires

Patent metadata

Field	Value
Publication number	US-2020089836-A1
Application number	US-201816130693-A
Country	US
Kind code	A1
Filing date	Sep 13, 2018
Priority date	Sep 13, 2018
Publication date	Mar 19, 2020
Grant date	—

Abstract

A system, method and computer program product for extracting integrated circuit on-chip parasitic capacitance in semiconductor structures including structures formed according to a Self-Aligned Double Patterning (SADP) semiconductor manufacturing process. A method of calculating the capacitance of a conductive signal wire in a SADP layer whose adjacent wires or groups of wires are floating (not connected to a circuit or net and not signal carrying). Further, there is provided a system running an iterative method for accurately and efficiently eliminating a group of floating metals by eliminating one floating metal wire per iteration while extracting its corresponding on-chip parasitic coupling capacitance effect. Further, system and methods calculate parasitic capacitance calculation for an “isolated” wire(s) or a “semi-isolated wire” resulting from employing a Self-Aligned Double Patterning (SADP) processing technique. The system and method provides a capacitance calculation and circuit simulation solution without involving use of and without computing a capacitance matrix.

First claim

1 . A computer-implemented method for manufacturing a multi-level integrated circuit (IC), the method comprising:
accessing, using a computer system, a multi-level integrated circuit design layout; extracting, using the computing system, a parasitic capacitance of structures in said multi-level IC design layout, said structures including a wire level having a plurality of metal wires to be manufactured according to a self-aligned double-patterning (SADP) manufacturing process, said wire level situated above one or more lower layers of conductive structures and situated below one or more upper layers of conductive structures, said extracting resulting in a capacitive network of wires in said IC design layout; selecting a target metal wire from said plurality of metal wires at said wire level, said selected target metal wire having one or more parallel situated floating metal wires on at least one side thereof, said capacitive network comprising: capacitance component values for said target metal wire at said SADP metal wire layer, capacitance component values of said floating metal wires, a node of said selected target metal wire, and nodes of the floating metal wires; eliminating, using one or more processors of said computing system, the nodes of the floating metal wires from the capacitive network to reduce the size of the capacitive network; simulating, using a circuit simulator run at said computer system, a circuit performance involving the selected target metal wire of the capacitive network; and repeating, at the computing system, from said IC design layout, cycles of parasitic capacitance extracting, capacitance-network size reducing, and said simulating to optimize the multi-level IC design layout.

2 . The computer-implemented method of claim 1 , wherein said step of eliminating the nodes of said floating metal wires further comprises:
on each said at least one side of said target metal wire, successively eliminating from said capacitive network, using one or more processors of said computing system, each said one or more parallel situated floating metal wires adjacent on one side of said target metal wire at said metal layer until a second target current carrying metal wire is encountered and eliminating each said one or more parallel situated floating metal wires adjacent on another side of said at least one side of said target metal wire at said metal layer until a third target current carrying metal wire is encountered; and for each floating wire eliminated on each said at least one side, obtaining updated capacitive components for said target metal wire including a final updated coupling capacitive component between said target metal wire and the second target current carrying metal wire when all adjacent floating metal wires on said one side are eliminated and a final updated coupling capacitive component between said target metal wire and the third target current carrying metal wire when all adjacent floating metal wires on said another side are eliminated.

3 . The computer-implemented method of claim 2 , wherein said obtaining updated capacitive components for said target metal wire comprises:
at each successive eliminating of an adjacent floating metal wire on said one side of said target metal wire, computing updated capacitive components for both said target metal wire on one side of the floating wire and for a next adjacent metal wire on the other side of the floating wire being eliminated including an updated coupling capacitance between said target metal wire and the next adjacent floating metal wire on the other side of the floating wire being eliminated; and at each successive eliminating of an adjacent floating metal wire on said another side of said target metal wire, computing updated capacitive components for both said target metal wire on one side of the floating wire and for a next adjacent metal wire on the other side of the floating wire being eliminated including an updated coupling capacitance between said target metal wire and the next floating metal wire on the other side of the floating metal wire being eliminated.

4 . The computer-implemented method of claim 3 , wherein prior to said eliminating of an adjacent floating metal wire on either side of the target metal wire, the method further comprising:
using one or more processors of said computing system to compute capacitance components for said target metal wire, said computed capacitance components including a coupling capacitance between said target metal wire and conductive structures at each said one or more upper layers, a coupling capacitance between said target metal wire and conductive structures at each said one or more lower layers, a coupling capacitance between said target metal wire and a first floating metal wire on the same layer adjacent said target metal wire on one side, and a coupling capacitance between said target metal wire and a first floating metal wire on the same layer adjacent said target metal wire on another side.

5 . The computer-implemented method of claim 4 , wherein said obtaining updated capacitive components for said target metal wire comprises:
after each successive eliminating of a floating metal wire adjacent on said one side of said target metal wire, updating a coupling capacitance between said target metal wire and conductive structures at each said one or more upper layers, and a coupling capacitance between said target metal wire and conductive structures at each said one or more lower layers; and after each successive eliminating of a floating metal wire adjacent on said another side of said target metal wire, updating a coupling capacitance between said target metal wire and conductive structures at each said one or more upper layers, and a coupling capacitance between said target metal wire and conductive structures at each said one or more lower layers.

6 . The computer-implemented method of claim 5 , further comprising:
generating, by said one or more processors, a netlist representation for said IC design that excludes all said floating metal wires on said one side of said target metal wire at said layer and excludes all said floating metal wires on said another side of said target metal wire.

7 . The computer-implemented method as claimed in claim 6 , further comprising:
simulating, in an electronic design simulator, a performance of said IC circuit design, said simulator using said updated coupling capacitive component between said target metal wire and conductive structures at each said one or more upper layers, and conductive structures at said one or more lower layers, the final updated coupling capacitance between said target metal wire and second target wire on the same layer on said one side, and the final updated coupling capacitance between said target metal wire and said third target wire on the same layer on said another side.

8 . The computer-implemented method as claimed in claim 1 , wherein said updated capacitive components for said target metal wire includes one or more capacitance components attributable to said floating metal wire when treated as connected in said capacitive network prior to said eliminating, said method further comprising, for an adjacent floating metal wire in an SADP metal wire layer to be eliminated:
computing capacitance components for the adjacent floating metal wire to be eliminated, a respective computed capacitance component for said adjacent floating metal wire representing a capacitance between said adjacent floating metal wire and a respective metal wire at each said upper and lower layer metal wires, said capacitance components for the adjacent floating metal wire excluding said coupling capacitance component between said target metal wire and the adjacent floating me

Assignees

• IBM

Inventors

• Lu Ning
• Bittner Calvin

Classifications

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title

• G06F2119/10

  Noise analysis or noise optimisation · CPC title

• G06F30/367 Primary

  Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G03F1/70

  Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging · CPC title