System, Apparatus and Method for Utilizing Surface Mount Technology on Metal Substrates

Patent metadata

Field	Value
Publication number	US-2022408565-A1
Application number	US-202217857664-A
Country	US
Kind code	A1
Filing date	Jul 5, 2022
Priority date	Jun 15, 2017
Publication date	Dec 22, 2022
Grant date	—

Abstract

An electronic circuit, comprising: an integrated substrate structure comprising one or more electrically conductive traces comprising plating on a laser-etched, non-conductive isolated portion of the integrated substrate structure defining each electrically conductive trace; one or more electrically conductive pads at one or more predetermined positions along the one or more electrically conductive traces; and an electrical component surface mounted to the at least one electrically conductive pad with interconnect and bonding material.

First claim

What is claimed is:

1 . An electronic circuit, comprising:
an integrated substrate structure comprising one or more electrically conductive traces comprising plating on a laser-etched, non-conductive isolated portion of the integrated substrate structure defining each electrically conductive trace; one or more electrically conductive pads at one or more predetermined positions along the one or more electrically conductive traces; and an electrical component surface mounted to the at least one electrically conductive pad with interconnect and bonding material.

2 . The electronic circuit of claim 1 , wherein the plating on a laser-etched, non-conductive isolated portion comprises:
a non-conductive isolation layer portion having an activation ink printed in a pattern forming region of an insulating surface of the integrated substrate structure; a first metal layer formed on the non-conductive isolation layer; and a second metal layer formed on the first metal layer.

3 . The electronic circuit of claim 2 , wherein the plating on a laser-etched, non-conductive isolated portion is formed by removing part of the first metal layer along an outer periphery of the one or more electrically conductive traces to isolate the one or more electrically conductive traces of the first metal layer.

4 . The electronic circuit of claim 1 , wherein the non-conductive isolated portion is electrically non-conductive.

5 . The electronic circuit of claim 2 , wherein the integrated substrate structure includes a metal base layer and an insulating layer formed on the metal base layer to provide an insulating surface.

6 . The electronic circuit of claim 2 , wherein the activation ink includes N-methyl-2-pyrrolidone.

7 . The electronic circuit of claim 2 , further comprising:
a solder mask layer to cover the one or more electrically conductive traces.

8 . The electronic circuit of claim 7 , further comprising:
a protective layer covering pad areas not covered by the solder mask layer.

Assignees

• Jabil Inc

Inventors

• Wu Weiping (Aka Jonathan)
• Tura Ali Mohd Yusuf
• Samsudin Zambri

Classifications

• H05K3/182 Primary

  characterised by the patterning method · CPC title

• H05K2203/0709

  Catalytic ink or adhesive for electroless plating · CPC title

• C25D7/00

  Electroplating characterised by the article coated · CPC title

• C23C18/1653

  Two or more layers with at least one layer obtained by electroless plating and one layer obtained by electroplating · CPC title

• C23C18/1608

  from pretreatment step, i.e. selective pre-treatment · CPC title