Semiconductor structure and method for forming same

Patent metadata

Field	Value
Publication number	US-2022392902-A1
Application number	US-202217828232-A
Country	US
Kind code	A1
Filing date	May 31, 2022
Priority date	Jun 2, 2021
Publication date	Dec 8, 2022
Grant date	—

Abstract

A semiconductor structure and the method for forming the same are provided. The method includes: providing a substrate including an active region; forming a word line in the substrate including a first portion and a second portion located at the end of the first portion, wherein the second portion of the word line protrudes from the first portion of the word line along the direction perpendicular to the substrate; forming a dielectric layer covering the substrate; and etching the dielectric layer and a part of the substrate to simultaneously form a first contact hole exposing the second portion of the word line and a second contact hole exposing the active region. The invention reduces the etching time and improves the etching efficiency. It avoids an excessively large etching depth of the second contact hole, thereby reducing the damage to the active region and the leakage current inside the semiconductor structure.

First claim

What is claimed is:

1 . A method for forming a semiconductor structure, comprising:
providing a substrate, the substrate comprising an active region; forming a word line in the substrate, the word line comprising a first portion and a second portion located at an end of the first portion, wherein the second portion of the word line protrudes from the first portion of the word line along a direction perpendicular to the substrate; forming a dielectric layer covering the substrate; and etching the dielectric layer and a part of the substrate to simultaneously form a first contact hole exposing the second portion of the word line and a second contact hole exposing the active region.

2 . The method of claim 1 , wherein the substrate comprises a cell area and a peripheral area located outside the cell area, and the active region is located in the cell area of the substrate; and wherein forming the word line in the substrate comprises:
etching the substrate to form a groove extending across the cell area and to the peripheral area along a first direction parallel to the substrate; and filling the groove with a conductive material to form the first portion of the word line in the cell area and the second portion of the word line in the peripheral area.

3 . The method of claim 2 , wherein forming the first portion of the word line in the cell area and the second portion of the word line in the peripheral area comprises:
depositing a first conductive material in the groove and on a surface of the substrate to form a conductive layer covering the cell area and the peripheral area; and etching the conductive layer to form the first portion of the word line and the second portion of the word line.

4 . The method of claim 3 , wherein etching the conductive layer comprises:
forming a shielding layer covering a surface of the conductive layer located in the peripheral area; removing a part of the conductive layer on the surface of the substrate in the cell area, wherein a portion of the conductive layer remaining in the cell area serves as an initial first portion of the word line, and a portion of the conductive layer remaining in the peripheral area serves as an initial second portion of the word line; and back-etching a part of the initial first portion of the word line and a part of the initial second portion of the word line, wherein a portion of the initial first portion of the word line remaining in the groove of the cell area serves as the first portion of the word line, and a portion of the initial second portion of the word line remaining in the groove of the peripheral area serves as the second portion of the word line.

5 . The method of claim 3 , wherein before depositing the first conductive material in the groove and on the surface of the substrate, the method further comprises:
forming a diffusion barrier layer on an inner wall of the groove.

6 . The method of claim 4 , wherein the peripheral area is distributed around the cell area, and wherein forming the shielding layer covering the surface of the conductive layer located in the peripheral area comprises:
depositing a photoresist material in the peripheral area to form the shielding layer, the shielding layer covering the conductive layer located in the peripheral area and exposing the conductive layer located in the cell area.

7 . The method of claim 1 , wherein before forming the dielectric layer covering the substrate, the method further comprises:
forming a bit line on the substrate.

8 . The method of claim 7 , wherein forming the dielectric layer covering the substrate comprises:
depositing a dielectric material on the substrate to form the dielectric layer covering the surface of the substrate and the bit line.

9 . The method of claim 8 , wherein simultaneously forming the first contact hole exposing the second portion of the word line and the second contact hole exposing the active region comprises:
etching the dielectric layer and the substrate to simultaneously form the first contact hole exposing the second portion of the word line, the second contact hole exposing the active region, and a third contact hole exposing the bit line.

10 . The method of claim 9 , wherein the bit line extends from the cell area to the peripheral area, and wherein the third contact hole exposes the bit line in the peripheral area.

11 . The method of claim 9 , further comprising:
filling the first contact hole, the second contact hole, and the third contact hole with a second conductive material, and simultaneously forming a first contact plug in contact with the second portion of the word line, a second contact plug in contact with the active region, and a third contact plug in contact with the bit line.

12 . The method of claim 11 , further comprising:
forming a first peripheral circuit electrically connected to the first contact plug, a second peripheral circuit electrically connected to the second contact plug, and a third peripheral circuit electrically connected to the third contact plug.

13 . The method of claim 1 , wherein a ratio of a thickness of the second portion of the word line to a thickness of the first portion of the word line ranges from (7:4) to (7:6).

14 . A semiconductor structure, comprising:
a substrate comprising an active region; a word line in the substrate, the word line comprising a first portion and a second portion located at an end of the first portion, wherein the second portion of the word line protrudes from the first portion of the word line along a direction perpendicular to the substrate; a dielectric layer covering the substrate; a first contact plug penetrating the dielectric layer and a part of the substrate and in contact with the second portion of the word line; and a second contact plug penetrating at least the dielectric layer and in contact with the active region.

15 . The semiconductor structure of claim 14 , wherein the substrate comprises a cell area and a peripheral area located outside the cell area, and the active region is located in the cell area of the substrate, and wherein the first portion of the word line is located in the cell area, and the second portion of the word line is located in the peripheral area.

16 . The semiconductor structure of claim 14 , further comprising:
a groove located in the substrate; a diffusion barrier layer covering an inner wall of the groove; and a word line located on a surface of the diffusion barrier layer and filling the groove.

17 . The semiconductor structure of claim 15 , further comprising:
a bit line located on the substrate, wherein the dielectric layer covers a surface of the substrate and the bit line.

18 . The semiconductor structure of claim 17 , further comprising:
a third contact plug penetrating at least the dielectric layer and in contact with the bit line.

19 . The semiconductor structure of claim 18 , wherein the bit line extends from the cell area to the peripheral area; and wherein
the third contact plug is in contact with the bit line located in the peripheral area.

20 . The semiconductor structure of claim 19 , further comprising:
a first peripheral circuit, wherein the first contact plug has one end in contact with the second portion of the word line, and the other end electrically connected to the first peripheral circuit; a second peripheral circuit, wherein the second contact plug has one end in contact with the active region, and the other end electrically connected to the se

Assignees

• Changxin Memory Tech Inc

Inventors

• Bai Shijie
• Yu Yexiao
• Liu Zhongming

Classifications

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/083 Primary

  the openings being via holes penetrating underlying conductors · CPC title

• G11C11/4085

  Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge · CPC title