Power Semiconductor Device

Patent metadata

Field	Value
Publication number	US-2022375811-A1
Application number	US-202217741527-A
Country	US
Kind code	A1
Filing date	May 11, 2022
Priority date	May 19, 2021
Publication date	Nov 24, 2022
Grant date	—

Abstract

A power semiconductor device includes, an active area that conducts load current between first and second load terminal structures, a drift region, and a backside region that includes, inside the active area, first and second backside emitter zones one or both of which includes: first sectors having at least one first region of a second conductivity type contacting the second load terminal structure and a smallest lateral extension of at most 50 μm; and/or second sectors having a second region of the second conductivity type contacting the second load terminal structure and a smallest lateral extension of at least 50 μm. The emitter zones differ by at least of: the presence of first and/or second sectors; smallest lateral extension of first and/or second sectors; lateral distance between neighboring first and/or second sectors; smallest lateral extension of the first regions; lateral distance between neighboring first regions within the same first sector.

First claim

What is claimed is:

1 . A power semiconductor device, comprising:
a semiconductor body having a front side and a backside; a first load terminal structure coupled to the front side and a second load terminal structure coupled to the backside; an active area of the semiconductor body configured to conduct a load current between the first load terminal structure and the second load terminal structure; a drift region of the semiconductor body, the drift region having a first conductivity type and configured to conduct the load current; and a backside region of the semiconductor body, the backside region arranged at the backside and comprising, inside the active area, a first backside emitter zone and a second backside emitter zone, wherein the first backside emitter zone is arranged within the active area with greater distance to an outer border of the active area than the second backside emitter zone, wherein the first backside emitter zone comprises a plurality of first sectors each comprising at least one first region of a second conductivity type, the first region arranged in contact with the second load terminal structure, wherein the second backside emitter zone comprises a plurality of second sectors each comprising at least one second region of the second conductivity type, the second regions arranged in contact with the second load terminal structure, wherein a pitch defining a lattice constant along at least a first lateral direction is at least essentially equal in the first backside emitter zone and the second backside emitter zone, wherein the first backside emitter zone differs from the second backside emitter zone in a smallest lateral extension of the first sectors being greater than a smallest lateral extension of the second sectors.

2 . The power semiconductor device of claim 1 , wherein the first regions have a smallest lateral extension of at most 50 μm and/or the second regions have a smallest lateral extension of at least 50 μm.

3 . A power semiconductor device, comprising:
a semiconductor body having a front side and a backside; a first load terminal structure coupled to the front side and a second load terminal structure coupled to the backside; an active area of the semiconductor body configured to conduct a load current between the first load terminal structure and the second load terminal structure; a drift region of the semiconductor body, the drift region having a first conductivity type and configured to conduct the load current; and a backside region of the semiconductor body, the backside region arranged at the backside and comprising, inside the active area, a second backside emitter zone, wherein the second backside emitter zone comprises a plurality of second sectors each comprising at least one second region of the second conductivity type, the second regions arranged in contact with the second load terminal structure and each having a smallest lateral extension, wherein, along a thought line, for at least three neighboring second sectors their smallest lateral extension increases strictly monotonically.

4 . The power semiconductor device of claim 3 , wherein the second sectors are arranged according to a lattice with a pitch defining a lattice constant along at least a first lateral direction, and wherein the pitch is at least essentially constant for the at least three neighboring second regions along the thought line.

5 . The power semiconductor device of claim 3 , wherein for the at least three neighboring second regions, their smallest lateral extension increases with increasing distance to an outer border of the active area.

6 . The power semiconductor device of claim 3 , wherein an area extension of each of the first backside emitter zone and the second backside emitter zone amounts to at least 5% or even at least 10% of the active area.

7 . The power semiconductor device of claim 3 , wherein a lateral distance between neighboring first and/or second sectors amounts to at least 50 μm.

8 . The power semiconductor device of claim 3 , wherein a lateral distance between neighboring first sectors in the first emitter zone is at maximum three times the smallest lateral extension of the first sector and/or a lateral distance between neighboring second sectors in the second emitter zone is at maximum three times the smallest lateral extension of the second sectors.

9 . The power semiconductor device of claim 3 , wherein:
the first backside emitter zone comprises a plurality of first sectors each comprising a plurality of first regions; the first regions are arranged at a lateral distance from each other of at most three times the smallest lateral extension of the first regions; and the second backside emitter zone comprises a plurality of second sectors each comprising a second region having a smallest lateral extension of at least ten times the smallest lateral extension of the first regions.

10 . The power semiconductor device of claim 3 , wherein the backside region further comprises a third backside zone which comprises at least one region of the first conductivity type and a plurality of regions of the second conductivity type arranged in alternating order in contact with the second load terminal structure, the regions of the first conductivity type and/or the regions of the second conductivity type having a smallest lateral extension of at most 50 μm.

11 . The power semiconductor device of claim 10 , wherein the third backside zone is arranged in an edge termination region of the semiconductor body.

12 . The power semiconductor device of claim 10 , wherein the third backside zone is arranged below a gate runner electrode that is arranged at the front side.

13 . The power semiconductor device of claim 10 , wherein a lateral extension of the third backside zone amounts to at least 0.5 times a vertical thickness of the drift region.

14 . The power semiconductor device of claim 10 , wherein the backside region further comprises a spacer region laterally separating the second backside emitter zone from the third backside zone.

15 . The power semiconductor device of claim 14 , wherein a smallest lateral extension of the spacer region amounts to at least 0.5 times a vertical thickness of the drift region.

16 . The power semiconductor device of claim 3 , wherein:
the first backside emitter zone exhibits each of a first emitter efficiency and a first injection efficiency; the second backside emitter zone exhibits each of a second emitter efficiency and a second injection efficiency at the nominal current; the first emitter efficiency differs from the second emitter efficiency by at least 1%, and/or the first injection efficiency differs from the second injection efficiency by at least 5%, and/or an injected hole charge of the first backside emitter zone differs from an injected hole charge of the second backside emitter zone by at least 10%, and/or an average backside plasma concentration associated with the first backside emitter zone differs from an average backside plasma concentration associated with the second backside emitter zone by at least 5%.

17 . The power semiconductor device of claim 3 , wherein in a horizontal cross-section through the first backside emitter zone and/or the second backside emitter zone, regions of the second conductivity type exhibit at least one of: a circular configuration; a ring configuration; a stripe configuration; and a honeycomb configuration.

18 . The power semiconductor device of claim 3 , wherein the semiconductor body comprises a

Assignees

• Infineon Technologies Ag

Inventors

• Baburske Roman
• Hauf Moritz
• Schulze Hans-Joachim
• Schulze Holger
• Stoib Benedikt

Classifications

• H10W40/22 Primary

  characterised by their shape, e.g. having conical or cylindrical projections · CPC title

• H01L29/7813

  Electricity · mapped topic

• H01L23/367 Primary

  Electricity · mapped topic

• H01L29/7397

  Electricity · mapped topic

• H01L29/861

  Electricity · mapped topic