Integrated Memory Comprising Secondary Access Devices Between Digit Lines and Primary Access Devices

Patent metadata

Field	Value
Publication number	US-2022367465-A1
Application number	US-202217877628-A
Country	US
Kind code	A1
Filing date	Jul 29, 2022
Priority date	Aug 10, 2018
Publication date	Nov 17, 2022
Grant date	—

Abstract

Some embodiments include an integrated assembly having a primary access transistor. The primary access transistor has a first source/drain region and a second source/drain region. The first and second source/drain regions are coupled to one another when the primary access transistor is in an ON mode, and are not coupled to one another when the primary access transistor is in an OFF mode. A charge-storage device is coupled with the first source/drain region. A digit line is coupled with the second source/drain region through a secondary access device. The secondary access device has an ON mode and an OFF mode. The digit line is coupled with the charge-storage device only when both the primary access transistor and the secondary access device are in their respective ON modes.

First claim

1 .- 20 . (canceled)

21 . An integrated assembly, comprising:
a first transistor extending in a first direction and having first and second source/drain regions; and a second transistor extending in a second direction oriented 90 degrees different from the first direction, the second transistor comprising a third source/drain region coupled with the first source/drain region of the first transistor.

22 . The integrated assembly of claim 21 further comprising a digit line coupled to a fourth source/drain region of the second transistor.

23 . The integrated assembly of claim 21 further comprising a charge-storage device coupled to the second source/drain region of the first transistor.

24 . The integrated assembly of claim 23 wherein the first transistor and the charge-storage device together comprise a memory cell.

25 . The integrated assembly of claim 24 wherein the memory cell is one of many substantially identical memory cells within a DRAM array.

26 . The integrated assembly of claim 21 further comprising a third transistor sharing the first source/drain region of the first transistor.

27 . An integrated assembly, comprising:
a first transistor comprising first and second source/drain regions; and a second transistor comprising a gate, and third and fourth source/drain regions, the first and third source/drain regions are coupled to each other and the gate is coupled to a multiplexer.

28 . The integrated assembly of claim 27 wherein the first transistor extends in a first direction and the second transistor extends in a second direction different from the first direction.

29 . The integrated assembly of claim 27 wherein the multiplexer enables the second transistor to be independently controlled relative to the first transistor.

30 . The integrated assembly of claim 29 wherein the first and second transistors are incorporated into an array of other transistors, and wherein the multiplexer enables the second transistor to be independently controlled relative to the array of other transistors.

31 . The integrated assembly of claim 27 further comprising a third transistor sharing the first source/drain region of the first transistor.

32 . An integrated assembly, comprising:
a first transistor comprising first and second source/drain regions; a second transistor sharing the first source/drain region with the first transistor and comprising a third source/drain region; and a third transistor comprising a fourth source/drain region coupled to the shared first source/drain region.

33 . The integrated assembly of claim 32 further comprising a pillar of material providing the coupling between the fourth and the shared first source/drain regions.

34 . The integrated assembly of claim 33 wherein the pillar of material comprises a channel and a fifth source/drain region of the third transistor.

35 . The integrated assembly of claim 33 wherein the pillar of material is coupled to a digit line.

36 . The integrated assembly of claim 33 wherein the pillar of material comprises at least one of the following compositions: a metal; a metal-containing composition; and a semiconductor material.

37 . The integrated assembly of claim 33 wherein the pillar of material comprises at least two of the following compositions: a metal; a metal-containing composition; and a semiconductor material.

38 . The integrated assembly of claim 27 wherein at least two of the first, second and third transistors extend in different directions.

Assignees

• Micron Technology Inc

Inventors

• Derner Scott J
• Ingalls Charles L

Classifications

• G11C11/4063 Primary

  Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing · CPC title

• G11C11/404

  with one charge-transfer gate, e.g. MOS transistor, per cell · CPC title

• G11C11/403

  with charge regeneration common to a multiplicity of memory cells, i.e. external refresh · CPC title

• G11C2207/002

  Isolation gates, i.e. gates coupling bit lines to the sense amplifier · CPC title

• G11C11/4091 Primary

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title