Resistive memory system, driver circuit thereof and method for setting resistance thereof

Patent metadata

Field	Value
Publication number	US-9443588-B2
Application number	US-201514749651-A
Country	US
Kind code	B2
Filing date	Jun 25, 2015
Priority date	Oct 27, 2014
Publication date	Sep 13, 2016
Grant date	Sep 13, 2016

Abstract

A resistive memory system, a driver circuit thereof and a method for setting resistances thereof are provided. The resistive memory system includes a memory array, a row selection circuit, a first control circuit and a second control circuit. The memory array has a plurality of resistive memory cells. The row selection circuit is used for activating the resistive memory cells. The first control circuit and the second control circuit are coupled to the resistive memory cells. When each of resistive memory cells is set, the first control circuit and the second control circuit respectively provide a set voltage and a ground voltage to the each of resistive memory cells to form a set current, and the set current is clamped by at least one of the first control circuit and the second control circuit.

First claim

What is claimed is:

1. A driver circuit, adapted to drive a memory array having a plurality of resistive memory cells, the driver circuit comprising:
a row selection circuit, coupled to the resistive memory cells, and activating the resistive memory cells;
a first control circuit, coupled to the resistive memory cells, and providing a set voltage and a ground voltage; and
a second control circuit, coupled to the resistive memory cells, and providing a reset voltage and the ground voltage,
wherein when each of the resistive memory cells is set, the first control circuit provides the set voltage to each of the resistive memory cells, and the second control circuit provides the ground voltage to each of the resistive memory cells to form a set current, and the set current is clamped by at least one of the first control circuit and the second control circuit,
wherein the resistive memory cells are coupled to the row selection circuit through a plurality of row selection lines, the resistive memory cells are coupled to the first control circuit through a plurality of bit lines, and the resistive memory cells are coupled to the second control circuit through a plurality of source lines, wherein the row selection circuit is used for enabling one of the row selection lines,
wherein the first control circuit comprises a first current clamping unit for providing the set voltage and clamping the set current, the first current clamping unit comprises:
a first P-type transistor, having a first terminal receiving the set voltage, a second terminal coupled to the corresponding bit line and a control terminal; and
a first multiplexer, coupled to the control terminal of the first P-type transistor, and receiving a first current clamping voltage, an operation voltage and a set signal, and providing the first current clamping voltage or the operation voltage to the control terminal of the first P-type transistor according to the set signal, wherein the first current clamping voltage is used for clamping the set current.

2. The driver circuit as claimed in claim 1 , wherein the first control circuit further comprises:
a first N-type transistor, having a first terminal coupled to the corresponding bit line, a second terminal receiving the ground voltage and a control terminal receiving an inverted signal of the set signal.

3. The driver circuit as claimed in claim 1 , wherein the second control circuit comprises:
a second P-type transistor, having a first terminal receiving the reset voltage, a second terminal coupled to the corresponding source line and a control terminal receiving an inverted signal of the reset signal; and
a second N-type transistor, having a first terminal coupled to the corresponding source line, a second terminal receiving the ground voltage and a control terminal receiving the inverted signal of the reset signal.

4. The driver circuit as claimed in claim 1 , wherein the second control circuit comprises a second current clamping unit for providing the ground voltage and clamping the set current.

5. The driver circuit as claimed in claim 4 , wherein the second current clamping unit comprises:
a third N-type transistor, having a first terminal coupled to the corresponding source line, a second terminal receiving the ground voltage and a control terminal; and
a second multiplexer, coupled to the control terminal of the third N-type transistor, and receiving a second current clamping voltage, the ground voltage and a set signal, and providing the second current clamping voltage or the ground voltage to the control terminal of the third N-type transistor according to the set signal, wherein the second current clamping voltage is used for clamping the set current.

6. The driver circuit as claimed in claim 5 , wherein the second control circuit further comprises:
a third P-type transistor, having a first terminal receiving the reset voltage, a second terminal coupled to the corresponding source line and a control terminal receiving an inverted signal of a reset signal.

7. The driver circuit as claimed in claim 1 , wherein the source lines are divided into a plurality of groups, and the source lines of each of the groups are coupled to each other for coupling to the second control circuit.

8. The driver circuit as claimed in claim 1 , wherein each of the resistive memory cells comprises:
a resistive memory element, coupled to the corresponding bit line, and setting an resistance thereof according to the set voltage and the reset voltage; and
a switch transistor, having a first terminal coupled to the resistive memory element, a second terminal coupled to the corresponding source line and a control terminal coupled to the corresponding row selection line.

9. The driver circuit as claimed in claim 8 , wherein further comprising:
a third control circuit, providing a bulk control voltage to a bulk terminal of the switch transistor of each of the resistive memory cells.

10. A resistive memory system, comprising:
a memory array, having a plurality of resistive memory cells; and
the driver circuit as claimed in claim 1 , coupled to the resistive memory cells, and driving the resistive memory cells.

11. A method for setting resistance of a resistive memory system, adapted to the resistive memory system having a plurality of resistive memory cells, and the method for setting resistance comprising:
determining whether each of the resistive memory cells is set;
providing a set voltage to each of the resistive memory cells through a first control circuit when each of the resistive memory cells is set, and providing a ground voltage to each of the resistive memory cells through a second control circuit to form a set current, wherein the set current is clamped by at least one of the first control circuit and the second control circuit; and
controlling the first control circuit to provide an inhibit voltage to each of the resistive memory cells when each of the resistive memory cells is not set,
wherein the second control circuit comprises a first current clamping unit, and the step of providing the ground voltage to each of the resistive memory cells through the second control circuit comprises:
providing the ground voltage to each of the resistive memory cells through the first current clamping unit of the second control circuit, so as to clamp the set current.

12. The method for setting resistance of the resistive memory system as claimed in claim 11 , wherein the first control circuit comprises a second current clamping unit, and the step of providing the set voltage to each of the resistive memory cells through the first control circuit comprises:
providing the set voltage to each of the resistive memory cells through the second current clamping unit of the first control circuit, so as to clamp the set current.

13. The method for setting resistance of the resistive memory system as claimed in claim 12 , wherein the second current clamping unit is coupled to each of the resistive memory cells through a bit line, and the method for setting resistance further comprises:
detecting a voltage level of the bit line;
controlling the second current clamping unit to transmit the set voltage without current clamping when the voltage level of the bit line is smaller than a write level;
controlling the second current clamping unit to clamp the set current when the voltage level of the bit line is greater than or equal to the write level.

14. A driver circuit, adapted to drive a memory array having a plurality of resistive memory cells, the driver circuit comprising:
a row selection circuit, coupled to the resistive memory cells,

Assignees

• Ind Tech Res Inst

Inventors

• Tseng Pei-Ling
• Kuo Chia-Chen
• Sheu Shyh-Shyuan
• Chang Meng-Fan

Classifications

• G11C13/0097 Primary

  Erasing, e.g. resetting, circuits or methods · CPC title

• G11C13/0061

  Timing circuits or methods · CPC title

• G11C13/0026

  Bit-line or column circuits · CPC title

• G11C2213/79

  Array wherein the access device being a transistor · CPC title

• G11C13/0023

  Address circuits or decoders · CPC title