Semiconductor package structure and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-2022367384-A1
Application number	US-202117321139-A
Country	US
Kind code	A1
Filing date	May 14, 2021
Priority date	May 14, 2021
Publication date	Nov 17, 2022
Grant date	—

Abstract

A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a substrate, a semiconductor device, an encapsulant, a balance structure, and a warpage-resistant layer. The semiconductor device is disposed on the substrate. The encapsulant encapsulates the semiconductor device. The balance structure is on the semiconductor device and contacting the encapsulant. The warpage-resistant layer is between the semiconductor device and the balance structure. The encapsulant contacts a lateral surface of the warpage-resistant layer.

First claim

What is claimed is:

1 . A semiconductor package structure, comprising:
a substrate; a semiconductor device disposed on the substrate; an encapsulant encapsulating the semiconductor device; a balance structure on the semiconductor device and contacting the encapsulant; and a warpage-resistant layer between the semiconductor device and the balance structure, wherein the encapsulant contacts a lateral surface of the warpage-resistant layer.

2 . The semiconductor package structure as claimed in claim 1 , wherein a geometric central line of the balance structure substantially aligns to a geometric central line of the substrate.

3 . The semiconductor package structure as claimed in claim 1 , wherein the encapsulant comprises a first portion engaged with the balance structure.

4 . The semiconductor package structure as claimed in claim 3 , wherein the encapsulant further comprises a second portion engaged with the substrate.

5 . The semiconductor package structure as claimed in claim 1 , wherein the substrate is a leadframe comprising a plurality of leads, and a bottom surface of the encapsulant is lower than a top surface of the leads.

6 . The semiconductor package structure as claimed in claim 1 , wherein the balance structure comprises at least one opening, and a portion of the encapsulant is filled in the opening.

7 . The semiconductor package structure as claimed in claim 6 , wherein an upper surface of the portion of the encapsulant is higher than a bottom surface of the balance structure.

8 . The semiconductor package structure as claimed in claim 1 , wherein the lateral surface of the warpage-resistant layer substantially aligns to a lateral surface of the semiconductor device.

9 . The semiconductor package structure as claimed in claim 1 , further comprises a binder adhering the warpage-resistant layer to the balance structure.

10 . The semiconductor package structure as claimed in claim 1 , further comprising a protection layer on at least one of an upper surface of the balance structure and one of a bottom surface of the substrate.

11 . A semiconductor package structure, comprising:
a substrate; a semiconductor device disposed on the substrate; an encapsulant encapsulating the substrate and the semiconductor device; and a heat dissipation structure disposed on the semiconductor device and the encapsulant, wherein a first distance between the heat dissipation structure and the semiconductor device is greater than a second distance between the heat dissipation structure and the encapsulant.

12 . The semiconductor package structure as claimed in claim 11 , further comprising a warpage-resistant layer disposed on a back surface of the semiconductor device, wherein a thickness of the warpage-resistant layer is equal to or less than the first distance.

13 . The semiconductor package structure as claimed in claim 12 , wherein the encapsulant covers an interface between the semiconductor device and the warpage-resistant layer.

14 . The semiconductor package structure as claimed in claim 12 , further comprises a binder adhering the warpage-resistant layer to the heat dissipation structure, wherein a sum of a thickness of the binder and the thickness of the warpage-resistant layer is substantially equal to the first distance.

15 . The semiconductor package structure as claimed in claim 11 , wherein the second distance is substantially 0.

16 . The semiconductor package structure as claimed in claim 11 , wherein the heat dissipation structure comprises a plurality of portions defining at least one through hole, and a portion of the encapsulant is disposed into the through hole.

17 . The semiconductor package structure as claimed in claim 11 , wherein the substrate further comprises a wettable flank recessed from a bottom surface and a lateral surface of the substrate.

18 . A method of manufacturing a semiconductor package structure, comprising:
forming a warpage-resistant layer on a semiconductor device; disposing the semiconductor device on a substrate; disposing a balance structure on the semiconductor device; and encapsulating the semiconductor device after disposing the balance structure.

19 . The method as claimed in claim 18 , wherein the balance structure has at least one through hole, the method further comprising:
encapsulating the semiconductor device by providing an encapsulant through the through hole of the balance structure; and disposing the substrate on a carrier prior to encapsulating the semiconductor device, wherein the carrier is configured as a stop layer for the encapsulant.

20 . The method as claimed in claim 18 , the method further comprising:
encapsulating the semiconductor device by providing an encapsulant from the substrate towards the semiconductor device, wherein the balance structure is configured as a stop layer for the encapsulant.

Assignees

• Advanced Semiconductor Eng

Inventors

• Yen You-Lung
• Appelt Bernd Karl
• Essig Kay Stefan

Classifications

• H10W74/111

  the semiconductor body being completely enclosed · CPC title

• H10W74/01

  Manufacture or treatment · CPC title

• H10W70/424

  Cross-sectional shapes (H10W70/481 takes precedence) · CPC title

• H10W40/77

  Auxiliary members characterised by their shape · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title