Electronic circuit comprising transistor and resistor

Patent metadata

Field	Value
Publication number	US-2022359578-A1
Application number	US-202017636083-A
Country	US
Kind code	A1
Filing date	Aug 19, 2020
Priority date	Aug 21, 2019
Publication date	Nov 10, 2022
Grant date	—

Abstract

A method of manufacturing an electronic circuit (or circuit module) (100) is disclosed. The electronic circuit comprises a transistor (1) and a resistor (2), the transistor comprising a source terminal (11), a drain terminal (12), a gate terminal (13), and a first body (10) of material providing a controllable semi-conductive channel between the source and drain terminals, and the resistor comprises a first resistor terminal (21), a second resistor terminal (22), and a second body (20) of material providing a resistive current path between the first resistor terminal and the second resistor terminal. The method comprises: forming the first body (10); and forming the second body (20), wherein the first body comprises a first quantity (100) of a metal oxide and the second body comprises a second quantity (200) of said metal oxide. Corresponding electronic circuits are disclosed.

First claim

1 . An electronic circuit (or circuit module) ( 100 ) comprising a transistor ( 1 ) and a resistor ( 2 ),
the transistor comprising a source terminal ( 11 ), a drain terminal ( 12 ), a gate terminal ( 13 ), and a first body ( 10 ) of material providing a controllable semiconductive channel between the source and drain terminals, the resistor comprising a first resistor terminal ( 21 ), a second resistor terminal ( 22 ), and a second body ( 20 ) of material providing a resistive current path between the first resistor terminal and the second resistor terminal, wherein said first body ( 10 ) of material comprises a metal oxide (e.g. comprises a first quantity of said metal oxide) and said second body ( 20 ) of material comprises said metal oxide (e.g. comprises a second quantity of said metal oxide).

2 . An electronic circuit in accordance with claim 1 , further comprising first and second voltage supply rails ( 61 , 62 ), and wherein said resistor is a load resistor connected in series between one of the source and drain terminals ( 11 , 12 ) and one of said voltage supply rails.

3 . An electronic circuit in accordance with 2 , wherein one of said first and second voltage supply rails is a ground rail and the other is a constant voltage supply rail.

4 . An electronic circuit in accordance with any preceding claim, wherein said second body ( 20 ) of material comprises a dopant.

5 . An electronic circuit in accordance with claim 4 , wherein said first body ( 10 ) of material does not comprise said dopant.

6 . An electronic circuit in accordance with any one of claims 1 to 3 , wherein said first body ( 10 ) of material comprises a dopant in a first range of concentrations, and said second body ( 20 ) of material comprises said dopant in a second range of concentrations.

7 . An electronic circuit in accordance with claim 6 , wherein said second range is higher than said first range.

8 . An electronic circuit in accordance with claim 6 , wherein said second range is lower than said first range.

9 . An electronic circuit in accordance with any preceding claim, wherein each of the first and second bodies ( 10 , 20 ) comprises a respective layer, film, or sheet of said metal oxide.

10 . An electronic circuit in accordance with claim 9 , wherein each said layer, film, or sheet has a thickness in the range 1 to 200 nm (for example in the range 5 to 50 nm).

11 . An electronic circuit in accordance with claim 9 or claim 10 , wherein each said layer, film, or sheet has the same thickness.

12 . An electronic circuit in accordance with any one of claims 9 to 11 , wherein each said layer, film, or sheet is flat (planar).

13 . An electronic circuit in accordance with claim 12 , wherein the first and second bodies are coplanar.

14 . An electronic circuit in accordance with claim 12 , wherein the first body lies in a first plane and the second body lies in a second plane, the second plane being parallel to said first plane.

15 . An electronic circuit in accordance with any one of claims 9 to 14 claim 6 , wherein the second body has a sheet resistance value in the range 25 kOhm/sq to 20 MOhm/sq (e.g. in the range 50 kOhm/sq to 10 MOhm/sq).

16 . An electronic circuit in accordance with any preceding claim, wherein each of the first and second bodies is substantially transparent to electromagnetic radiation in the range visible to the naked human eye.

17 . An electronic circuit in accordance with any preceding claim, wherein the circuit (or circuit module) comprises a substrate ( 5 ) arranged to support, directly or indirectly, each of the transistor ( 1 ) and the resistor ( 2 ).

18 . An electronic circuit in accordance with claim 17 , wherein the substrate is flexible.

19 . An electronic circuit in accordance with any preceding claim, wherein the circuit is flexible.

20 . An electronic circuit in accordance with any preceding claim, wherein said metal oxide is Indium Gallium Zinc Oxide, IGZO.

21 . An electronic circuit in accordance with any preceding claim, wherein the resistor ( 2 ) exhibits a resistance between its terminals ( 21 , 22 ) in the range 10 ohm to 10 MOhm (for example 100 ohm or 1 kOhm to 1 or 10 MOhm) at room temperature.

22 . An electronic circuit in accordance with any preceding claim, further comprising a second resistor ( 3 ) comprising first and second terminals ( 31 , 32 ) and a third body ( 30 ) of material providing a resistive current path between said terminals, wherein said third body of material comprises said metal oxide (e.g. comprises a third quantity of said metal oxide).

23 . An electronic circuit in accordance with claim 22 , wherein each of the second and third bodies is flat (planar), wherein the second body lies in a second plane and the third body lies in a third plane, said third plane being parallel to said second plane.

24 . An electronic circuit in accordance with claim 22 or claim 2323 , wherein said first and second resistors exhibit different resistances at room temperature.

25 . An electronic circuit in accordance with claim 24 , wherein said second body of material comprises a dopant in a second range of concentrations, and said third body of material comprises said dopant in a third range of concentrations, said second range being different from said third range.

26 . A method of manufacturing an electronic circuit (or circuit module)( 100 ) comprising a transistor ( 1 ) and a resistor ( 2 ), the transistor comprising a source terminal ( 11 ), a drain terminal ( 12 ), a gate terminal ( 13 ), and a first body ( 10 ) of material providing a controllable semiconductive channel between the source and drain terminals, and the resistor comprising a first resistor terminal ( 21 ), a second resistor terminal ( 22 ), and a second body ( 20 ) of material providing a resistive current path between the first resistor terminal and the second resistor terminal, the method comprising:
forming the first body ( 10 ); and forming the second body ( 20 ), wherein the first body comprises a first quantity ( 100 ) of a metal oxide and the second body comprises a second quantity ( 200 ) of said metal oxide.

27 . A method in accordance with claim 26 , wherein forming the first body comprises forming said first quantity of said metal oxide, and forming the second body comprises forming said second quantity of said metal oxide.

28 . A method in accordance with claim 27 , wherein forming said first quantity comprises forming said first quantity ( 100 ) directly or indirectly on a first region ( 51 ) of a substrate, and forming said second quantity comprises forming said second quantity ( 200 ) directly or indirectly on a second region ( 52 ) of the substrate.

29 . A method in accordance with claim 27 or claim 28 , wherein said forming of said first quantity comprises forming said first quantity ( 100 ) using a technique selected from a list comprising: physical deposition; physical vapour deposition (PVD); chemical deposition; chemical vapour deposition (CVD); atomic layer deposition (ALD); physical-chemical deposition;
evaporation; sputtering; sol-gel techniques; chemical bath deposition; spray pyrolysis; plating techniques; pulsed laser deposition (PLD); solution processing; and spin coating.

30 . A method in accordance with any one of claims 27 to 29 , wherein sai

Assignees

• Pragmatic Printing Ltd

Inventors

• Price Richard
• Ramsdale Catherine
• Downs Peter Fergus

Classifications

• H10P14/3434

  being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424) · CPC title

• H10D84/01

  Manufacture or treatment · CPC title

• H02M7/003

  Constructional details, e.g. physical layout, assembly, wiring or busbar connections · CPC title

• H01C17/28

  adapted for applying terminals · CPC title

• H01C1/14

  Terminals or tapping points specially adapted for resistors; Arrangements of terminals or tapping points on resistors · CPC title