Semiconductor package structure and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-2022328416-A1
Application number	US-202117225832-A
Country	US
Kind code	A1
Filing date	Apr 8, 2021
Priority date	Apr 8, 2021
Publication date	Oct 13, 2022
Grant date	—

Abstract

A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a substrate and a first passive device. The substrate has a first surface and a second surface opposite to the first surface. The first passive device includes a first terminal and a second terminal, wherein the first terminal is closer to the first surface than to the second surface, and the second terminal is closer to the second surface than to the first surface.

First claim

What is claimed is:

1 . A semiconductor package structure, comprising:
a substrate having a first surface and a second surface opposite to the first surface; and a first passive device embedded in the substrate, wherein the first passive device comprises a first terminal and a second terminal, wherein the first terminal is closer to the first surface than to the second surface, and the second terminal is closer to the second surface than to the first surface.

2 . The semiconductor package structure of claim 1 , further comprising:
a conductive wire bonded on the second surface and electrically connected to the first terminal.

3 . The semiconductor package structure of claim 2 , further comprising:
a conductive wire-bonding-protection layer disposed between the second terminal and the conductive wire.

4 . The semiconductor package structure of claim 1 , further comprising:
a second device electrically connected to the first passive device.

5 . The semiconductor package structure of claim 4 , wherein the second device is electrically connected to the first passive device in parallel.

6 . The semiconductor package structure of claim 5 , further comprising:
a third device electrically connected to the first passive device or the second device in series.

7 . The semiconductor package structure of claim 4 , wherein the second device electrically connected to the first passive device in series.

8 . The semiconductor package structure of claim 7 , further comprising:
a third device electrically connected to the second device and the first passive device in series.

9 . The semiconductor package structure of claim 4 , wherein the second device is disposed on the second surface of the substrate.

10 . The semiconductor package structure of claim 9 , wherein the second device comprises a first terminal and a second terminal, and an arrangement direction of the first terminal and the second terminal of the second device is substantially perpendicular to an arrangement direction of the first terminal and the second terminal of the first passive device.

11 . The semiconductor package structure of claim 9 , wherein an arrangement direction of the first terminal and the second terminal of the second device is substantially parallel to an arrangement direction of the first terminal and the second terminal of the first passive device.

12 . The semiconductor package structure of claim 4 , further comprising:
a pattern trace disposed on the second surface of the substrate, and the first passive device is electrically connected to the second device through the pattern trace.

13 . The semiconductor package structure of claim 12 , further comprising:
a conductive wire disposed on the pattern trace, and the first passive device is electrically connected to the second device through the conductive wire.

14 . The semiconductor package structure of claim 12 , wherein an active surface of the second device faces the second surface of the substrate, and the second device includes a plurality of electrical connectors disposed on the active surface of the second device, and the first passive device is electrically connected to the second device through the electrical connectors.

15 . The semiconductor package structure of claim 4 , further comprising:
a third device disposed on the second surface of the substrate, wherein the second device is electrically connected to the first passive device through the third device.

16 . The semiconductor package structure of claim 4 , further comprising:
a third device embedded in the substrate and electrically connected to the first passive device.

17 . A semiconductor package structure, comprising:
a substrate having a first surface and a second surface; a first passive device embedded in the substrate; and a first conductive element disposed on the first surface of the substrate; and a device disposed on the second surface of the substrate, wherein the first conductive element is electrically connected to the device through the first passive device.

18 . The semiconductor package structure of claim 17 , wherein the first passive device comprises a first terminal and a second terminal opposite to the first terminal, and the first terminal is closer to the first surface than the second terminal is.

19 . A method of manufacturing a semiconductor package structure, comprising:
providing a substrate having a first surface, a second surface and a first passive device in the substrate, wherein the first passive device has a first terminal and a second terminal opposite to the first terminal, and the first terminal is closer to the first surface than the second terminal is; and providing a second device, wherein the second device is electrically connected to the first passive device.

20 . The method of claim 19 , further comprising:
forming a dielectric layer on the second surface of the substrate; forming an opening of the dielectric layer to expose the second terminal of the first passive device by an energy beam operation; and forming a conductive wire-bonding-protection layer on the second terminal of the first passive device.

Assignees

• Advanced Semiconductor Eng

Inventors

• Yen You-Lung
• Appelt Bernd Karl
• Essig Kay Stefan

Classifications

• H10W90/759

  between a chip and a laterally-adjacent discrete passive device · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title

• H10W74/016

  using moulds · CPC title

• H10W72/075

  of bond wires · CPC title