Phase coherent frequency synthesis

Patent metadata

Field	Value
Publication number	US-2022278687-A1
Application number	US-202217689605-A
Country	US
Kind code	A1
Filing date	Mar 8, 2022
Priority date	Mar 1, 2021
Publication date	Sep 1, 2022
Grant date	—

Abstract

Techniques are provided for phase coherent frequency synthesis. An embodiment includes a first phase accumulator to accumulate a frequency control word (FCW) at a clocked rate to produce a first digital phase signal representing phase data corresponding to phase points on a first sinusoidal waveform. The embodiment also includes a second phase accumulator to produce an incrementing reference count at the clocked rate and multiply it by the FCW to produce a second digital phase signal representing phase data corresponding to phase points on a second sinusoidal waveform. The multiplication is performed in response to change in the FCW. The embodiment further includes a multiplexer to select between the first and second digital phase signals based on completion of the multiplication. The embodiment also includes a phase-to-amplitude converter to generate digital amplitude data corresponding to the phase points on a sinusoidal waveform associated with the selected digital phase signal.

First claim

What is claimed is:

1 . A phase coherent fractional-N phase locked loop (PLL) device comprising:
a fractional-N PLL circuit; a coherent phase generator circuit coupled to the fractional-N PLL circuit comprising:
a first phase accumulator configured to accumulate a fractional divide control word in response to a reference clock signal to produce a first digital phase signal;
a second phase accumulator configured to produce an incrementing reference count in response to the reference clock signal and configured to multiply the incrementing reference count by the fractional divide control word, the multiplication performed in response to detection of a change in the fractional divide control word, to produce a second digital phase signal; and
a multiplexer configured to provide the second digital phase signal as a selected digital phase signal in response to detected completion of the multiply, otherwise to provide the first digital phase signal as the selected digital phase signal; and
an overflow detection circuit coupled to the coherent phase generator circuit and configured to generate a carry bit based on detection of an overflow of the selected digital phase signal, the carry bit to control fractional switching of the fractional-N PLL circuit to maintain phase coherence between output signals of the fractional-N PLL circuit, alternating between a first output frequency and a second output frequency.

2 . The phase coherent fractional-N PLL device of claim 1 , wherein the fractional-N PLL circuit further comprises:
a fractional-N divider configured to perform a fractional division of the output signal of the fractional-N PLL circuit based on the carry bit to generate a fractionally divided output signal; a phase detector coupled to the fractional-N divider and configured to generate a phase adjustment signal based on a phase comparison of the reference clock signal to the fractionally divided output signal; a loop filter coupled to the phase detector and configured to smooth the phase adjustment signal; and a voltage controlled oscillator coupled to the loop filter and configured to generate an analog sinusoidal signal as the output signal of the fractional-N PLL circuit based on the smoothed phase adjustment signal.

3 . The phase coherent fractional-N PLL device of claim 1 , wherein the coherent phase generator circuit further comprises a summer configured to receive an adjustable phase offset and to add the adjustable phase offset to the selected digital phase signal.

4 . The phase coherent fractional-N PLL device of claim 1 , wherein the coherent phase generator circuit further comprises a delay circuit configured to delay the incrementing reference count by a time delay associated with a pre-determined time required to generate the second digital phase signal.

5 . The phase coherent fractional-N PLL device of claim 1 , wherein the second phase accumulator further comprises a counter configured to increment in response to each clock pulse of the reference clock signal to produce the incrementing reference count.

6 . The phase coherent fractional-N PLL device of claim 5 , wherein the counter is configured to increment until the second phase accumulator steps through one complete phase cycle and then resets to zero.

7 . The phase coherent fractional-N PLL device of claim 5 , wherein the counter is configured to truncate overflows of the second phase accumulator according to a modulo operation.

8 . A multistage delta-sigma modulator (DSM) phase coherent fractional-N phase locked loop (PLL) device comprising:
a fractional-N PLL circuit; a first sigma stage; a second sigma stage coupled to the first sigma stage in a series cascade configuration, wherein each of the first and second sigma stages are configured to generate respective first carry-out bits and second carry-out bits, each of the first and second sigma stages comprising respective coherent phase generator circuits and overflow detection circuits; and a delta stage configured to generate a carry-sum of the first carry-out bits and the second carry-out bits and to subtract previously generated first carry-out bits, the carry-sum to control fractional switching of the fractional-N PLL circuit to maintain phase coherence between output signals of the fractional-N PLL circuit, alternating between a first output frequency and a second output frequency.

9 . The multistage DSM phase coherent fractional-N PLL device of claim 8 , wherein the coherent phase generator circuit comprises:
a first phase accumulator configured to accumulate a fractional divide control word in response to a reference clock signal to produce a first digital phase signal; a second phase accumulator configured to produce an incrementing reference count in response to the reference clock signal and configured to multiply the incrementing reference count by the fractional divide control word, the multiplication performed in response to detection of a change in the fractional divide control word, to produce a second digital phase signal; and a multiplexer configured to provide the second digital phase signal as a selected digital phase signal in response to detected completion of the multiply, otherwise to provide the first digital phase signal as the selected digital phase signal.

10 . The multistage DSM phase coherent fractional-N PLL device of claim 9 , wherein the overflow detection circuit is configured to generate the respective first carry-out bits and second carry-out bits based on detection of an overflow of the selected digital phase signal.

11 . The multistage DSM phase coherent fractional-N PLL device of claim 9 , wherein the fractional-N PLL circuit further comprises:
a multi-modulus divider configured to perform a fractional division of the output signal of the fractional-N PLL circuit based on the carry-sum to generate a fractionally divided output signal; a phase detector coupled to the multi-modulus divider and configured to generate a phase adjustment signal based on a phase comparison of the reference clock signal to the fractionally divided output signal; a loop filter coupled to the phase detector and configured to smooth the phase adjustment signal; and a voltage controlled oscillator coupled to the loop filter and configured to generate an analog sinusoidal signal as the output signal of the fractional-N PLL circuit based on the smoothed phase adjustment signal.

12 . The multistage DSM phase coherent fractional-N PLL device of claim 9 , wherein the coherent phase generator circuit further comprises a delay circuit configured to delay the incrementing reference count by a time delay associated with a pre-determined time required to generate the second digital phase signal.

13 . The multistage DSM phase coherent fractional-N PLL device of claim 9 , wherein the second phase accumulator further comprises a counter configured to increment in response to each clock pulse of the reference clock signal to produce the incrementing reference count.

14 . The multistage DSM phase coherent fractional-N PLL device of claim 13 , wherein the counter is configured to increment until the second phase accumulator steps through one complete phase cycle and then resets to zero.

Assignees

• Bae Sys Inf & Elect Sys Integ

Inventors

• Turner Steven E
• Cali Joseph D

Classifications

• H03L7/1976

  using a phase accumulator for controlling the counter or frequency divider · CPC title

• H03M7/3022 Primary

  having multiple quantisers arranged in cascaded loops, each of the second and further loops processing the quantisation error of the loop preceding it, i.e. multiple stage noise shaping [MASH] type · CPC title

• H03M3/50

  Digital/analogue converters using delta-sigma modulation as an intermediate step (digital delta-sigma modulators per se H03M7/3004) · CPC title

• G06F1/022

  Waveform generators, i.e. devices for generating periodical functions of time, e.g. direct digital synthesizers (G06F1/025, G06F1/03 take precedence) · CPC title

• H03L7/093 Primary

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title