Fractional realignment techniques for PLLs

Patent metadata

Field	Value
Publication number	US-10784872-B1
Application number	US-201916572660-A
Country	US
Kind code	B1
Filing date	Sep 17, 2019
Priority date	Sep 17, 2019
Publication date	Sep 22, 2020
Grant date	Sep 22, 2020

Abstract

Systems, methods, and devices for fractional realignment are disclosed herein. A feedback divider generates a feedback dividing clock signal based on a controlling oscillator frequency. A delta-sigma modulator is coupled to the feedback divider and generates a dividing ratio to the feedback divider. An accumulating phase adjustor is coupled to the delta-sigma modulator and (i) determines a difference between a frequency tuning word (FCW) and the dividing ratio and (ii) generates a coarse tuning word and a fine tuning word. A digital-to-time converter (DTC) is coupled to the accumulating phase adjustor and generates a first clock frequency based on a reference clock frequency, the coarse tuning word and the fine tuning word. A realignment pulse generator is coupled to the DTC and generates a realignment clock based on the first clock frequency having a period that is the same as a period of the controlling oscillator frequency.

First claim

What is claimed is:

1. A device for fractional realignment, the circuit comprising:
a feedback divider configured to generate a feedback dividing clock signal based on a controlling oscillator frequency;
a delta-sigma modulator coupled to the feedback divider and configured to generate a dividing ratio to provide to the feedback divider based on the feedback dividing clock signal;
an accumulating phase adjustor coupled to the delta-sigma modulator, the accumulating phase adjustor configured to (i) determine a difference between a frequency tuning word (FCW) and the dividing ratio and (ii) generate a coarse tuning word and a fine tuning word;
a digital-to-time converter (DTC) coupled to the accumulating phase adjustor, the DTC configured to generate a first clock frequency based on a reference clock frequency, the coarse tuning word, and the fine tuning word; and
a realignment pulse generator coupled to the DTC, the realignment pulse generator configured to generate a realignment clock based on the first clock frequency having a period that is the same as a period of the controlling oscillator frequency.

2. The device of claim 1 , further comprising:
an oscillator coupled to the feedback divider, the oscillator configured to generate the controlling oscillator frequency; and
a delayed-lock loop (DLL) coupled to the DTC, the DLL configured to determine a period of the oscillator.

3. The device of claim 2 , wherein the feedback dividing circuit, the oscillator, the DLL, the delta-sigma modulator, the DTC, and the realignment pulse generator perform operations characterized by:
ACC n =ACC n+1 +(DIV_FROM_ DSM n −FCW )

where n represents time, ACC is an output of the accumulated phase adjustor, DIV_FROM_DSM is a combination of the dividing ratio and the FCW, and FCW is the frequency tuning word.

4. The device of claim 1 , wherein the frequency tuning word comprises a fractional component and an integer component.

5. The device of claim 1 , wherein the accumulating phase adjustor comprises:
a fraction subtraction block configured to identify the difference between the FCW and the dividing ratio;
an accumulator coupled to the fraction subtraction block, the accumulator configured to collect timings of operational cycles of the feedback dividing circuit, the oscillator, the DLL, the delta-sigma modulator, the DTC, and the realignment pulse generator;
a sign-to-unsign block couple to the accumulator, the sign-to-unsign block configured to generate an adjusted output;
a decoder block coupled to the sign-to-unsign block, the decoder block configured to generate the coarse tuning word and the fine tuning word based on the adjusted output of the sign-to-unsign block;
a reset block coupled between the accumulator and the fraction subtraction block, the reset block configured to inject pre-set code into the accumulator to replace existing numerals within the accumulator; and
an overflow/underflow detector coupled to the reset block and the accumulator, the overflow/underflow detector configured to provide the reset block with a detection signal signifying whether an overflow event or an underflow event has occurred within the accumulator.

6. The device of claim 5 , wherein the reset block and the overflow/underflow detector form a protection circuit, and operation of the protection circuit is characterized by the following equation:

ACC
n

=

ACC

n
+
1

+

{

[

[

Round_down
⁢

(

FCW
INT

4

)

+
1

]

*
40

+

(

FCW
INT

+

FCW
FRAC

)

*
10

]

+
80

}

where ACC is an output of the accumulated phase adjustor, n represents time, FCW INT is an integer component of the frequency tuning word, and FCW FRAC is a fractional component of the frequency tuning word.

7. The device of claim 1 , wherein the DTC modified a period of the reference clock frequency.

8. The device of claim 1 , wherein the DTC comprises:
a delay train having one or more delay elements configured to introduce latency within an input signal of the DTC;
a clock multiplexer configured to select a clock pair from the delay train for integer latency selection; and
a phase interpolator configured to select a fraction interval from the output of the clock multiplexer.

9. The device of claim 1 , wherein the reference clock frequency is the source of the realignment clock signal.

10. A method for fractional realignment comprising:
generating, by a feedback divider, a feedback dividing clock signal based on a controlling oscillator frequency;
generating, by a delta-sigma modulator, a dividing ratio to provide to the feedback divider based on the feedback dividing clock signal;
determining, by an accumulating phase adjustor coupled to the delta-sigma modulator, a difference between a frequency tuning word (FCW) and the dividing ratio;
generating, by the accumulating phase adjustor, a coarse tuning word and a fine tuning word;
generating, by a digital-to-time converter (DTC) coupled to the accumulating phase adjustor, a first clock frequency based on a reference clock frequency, the coarse tuning word, and the fine tuning word; and
generating, by a realignment pulse generator coupled to the DTC, a realignment clock based on the first clock frequency having a period that is the same as a period of the controlling oscillator frequency.

11. The method of claim 10 , further comprising:
generating, by an oscillator coupled to the feedback divider, the controlling oscillator frequency; and
determining, by a delayed-lock loop (DLL) coupled to the DTC, a period of the oscillator.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Tsai Tsung-Hsien
• Sheen Ruey-Bin
• Chang Chih-Hsien
• Hsieh Cheng-Hsiang

Classifications

• H03L7/085 Primary

  concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) · CPC title

• H03L7/1976

  using a phase accumulator for controlling the counter or frequency divider · CPC title

• H03L7/1806 Primary

  the frequency divider comprising a phase accumulator generating the frequency divided signal · CPC title

• H03L7/089

  the phase or frequency detector generating up-down pulses (H03L7/087 takes precedence) · CPC title

• H03L7/087

  using at least two phase detectors or a frequency and phase detector in the loop · CPC title