Nonvolatile memory device for increasing reliability of data detected through page buffer

Patent metadata

Field	Value
Publication number	US-2022246216-A1
Application number	US-202117499533-A
Country	US
Kind code	A1
Filing date	Oct 12, 2021
Priority date	Jan 29, 2021
Publication date	Aug 4, 2022
Grant date	—

Abstract

A nonvolatile memory device includes a memory cell array in a first semiconductor layer and including a first memory cell connected to a first word line and a first bit line and a second memory cell connected to the first word line and a second bit line; a page buffer circuit in a second semiconductor layer and including a first page buffer connected to the first bit line, and a second page buffer connected to the second bit line; and a page buffer controller in the second semiconductor layer. The page buffer controller controls the first and second page buffers so that a develop timing of a first sensing node of the first page buffer is different from a develop timing of a second sensing node of the second page buffer. The first page buffer is closer to a through electrode region than the second page buffer.

First claim

What is claimed is:

1 . A nonvolatile memory device comprising:
a memory cell array formed in a first semiconductor layer and including a first memory cell and a second memory cell, the first memory cell being connected to a first word line and a first bit line, and the second memory cell being connected to the first word line and a second bit line; a page buffer circuit formed in a second semiconductor layer located below the first semiconductor layer in a first direction, the page buffer circuit including a first page buffer and a second page buffer, the first page buffer being connected to the first bit line through a first through electrode passing through the first semiconductor layer and the second semiconductor layer in the first direction, and the second page buffer being connected to the second bit line through a second through electrode passing through the first semiconductor layer and the second semiconductor layer in the first direction; and a page buffer controller formed in the second semiconductor layer and configured to control the first page buffer and the second page buffer to respectively detect data values respectively stored in the first memory cell and the second memory cell, wherein a develop timing of a first sensing node of the first page buffer is different from a develop timing of a second sensing node of the second page buffer, wherein the first page buffer is closer to a through electrode region of the second semiconductor layer than the second page buffer, the through electrode region having the first through electrode and the second through electrode provided therein.

2 . The nonvolatile memory device of claim 1 , wherein the first through electrode is connected to the first bit line through a first upper contact of the first semiconductor layer and connected to the first page buffer through a first lower conductive line of the second semiconductor layer, and
the second through electrode is connected to the second bit line through a second upper contact of the first semiconductor layer and connected to the second page buffer through a second lower conductive line of the second semiconductor layer.

3 . The nonvolatile memory device of claim 1 , wherein a develop start point of the second sensing node is earlier than a develop start point of the first sensing node.

4 . The nonvolatile memory device of claim 1 , wherein a develop start point of the first sensing node is earlier than a develop start point of the second sensing node.

5 . The nonvolatile memory device of claim 1 , wherein a develop time of the second sensing node is less than a develop time of the first sensing node.

6 . The nonvolatile memory device of claim 1 , wherein a precharge timing of the first sensing node is different from a precharge timing of the second sensing node.

7 . The nonvolatile memory device of claim 1 , wherein the first page buffer and the second page buffer are arranged in a line in a second direction perpendicular to the first direction.

8 . A nonvolatile memory device comprising:
a memory cell array formed in a first semiconductor layer and including a plurality of memory cells connected in common to a first word line and respectively connected to bit lines; page buffers formed in a second semiconductor layer located below the first semiconductor layer in a first direction, the page buffers being respectively connected to the bit lines via through electrodes passing through the first semiconductor layer and the second semiconductor layer in the first direction; and a page buffer controller formed in the second semiconductor layer and configured to control the page buffers, based on different control timings, to respectively detect data values respectively stored in the plurality of memory cells, wherein the page buffers are arranged in a line in a second direction perpendicular to the first direction with respect to a through electrode region of the second semiconductor layer, the through electrode region having the through electrodes provided therein.

9 . The nonvolatile memory device of claim 8 , wherein the through electrodes are respectively connected to the bit lines through upper contacts of the first semiconductor layer and respectively connected to the page buffers through lower conductive lines of the second semiconductor layer.

10 . The nonvolatile memory device of claim 8 , wherein a first page buffer among the page buffers is closer to the through electrode region than a second page buffer among the page buffers, and
a develop timing of a first sensing node of the first page buffer is different from a develop timing of a second sensing node of the second page buffer.

11 . The nonvolatile memory device of claim 10 , wherein a develop start point of the second sensing node is earlier than a develop start point of the first sensing node.

12 . The nonvolatile memory device of claim 10 , wherein a develop start point of the first sensing node is earlier than a develop start point of the second sensing node.

13 . The nonvolatile memory device of claim 10 , wherein a develop time of the second sensing node is less than a develop time of the first sensing node.

14 . The nonvolatile memory device of claim 10 , wherein a develop time of the first sensing node does not overlap with a develop time of the second sensing node.

15 . A nonvolatile memory device comprising:
a memory cell array including a first memory cell and a second memory cell, the first and second memory cells being connected to a first word line; a page buffer circuit including a first page buffer and a second page buffer, the first page buffer being connected to the first memory cell through a first bit line, and the second page buffer being connected to the second memory cell through a second bit line; and a page buffer controller configured to control the first page buffer and the second page buffer to respectively detect data values respectively stored in the first memory cell and the second memory cell, wherein a develop timing of a first sensing node of the first page buffer is different from a develop timing of a second sensing node of the second page buffer, wherein the first page buffer is closer to the memory cell array than the second page buffer.

16 . The nonvolatile memory device of claim 15 , wherein a develop start point of the second sensing node is different from a develop start point of the first sensing node.

17 . The nonvolatile memory device of claim 15 , wherein a develop time of the first sensing node does not overlap with a develop time of the second sensing node.

18 . The nonvolatile memory device of claim 15 , wherein a first develop time of the first sensing node partially overlaps with a second develop time of the second sensing node.

19 . The nonvolatile memory device of claim 18 , wherein the second develop time is less than the first develop time.

20 . The nonvolatile memory device of claim 15 , wherein the first page buffer and the second page buffer are arranged in a line in an extension direction of the first bit line and the second bit line.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Myeongwoo
• Kim Chaehoon
• Kim Jihwan
• Song Jungho

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title

• G11C5/02

  Disposition of storage elements, e.g. in the form of a matrix array · CPC title