Integrated circuit with electrostatic discharge protection

Patent metadata

Field	Value
Publication number	US-2022223582-A1
Application number	US-202217706521-A
Country	US
Kind code	A1
Filing date	Mar 28, 2022
Priority date	Jul 30, 2020
Publication date	Jul 14, 2022
Grant date	—

Abstract

An integrated circuit includes a diode string, a first transistor, a second transistor, and a third transistor. The diode string is coupled between a first reference voltage pin and an input/output (I/O) pad. A first terminal of the second transistor is coupled to a first node, and a gate terminal of the second transistor is coupled to a second reference voltage pin. In response to a voltage at the first terminal of the second transistor being higher than a voltage at the gate terminal of the second transistor, the second transistor is configured to turn on the third transistor, and the third transistor is configured to transmit a voltage received from the first reference voltage pin to a gate terminal of the first transistor.

First claim

What is claimed is:

1 . An integrated circuit, comprising:
a diode string coupled between a first reference voltage pin and an input/output (I/O) pad; a first transistor coupled in parallel with the diode string, wherein a first terminal of the first transistor is coupled to the I/O pad; a second transistor, wherein a first terminal of the second transistor is coupled to a first node between two adjacent diodes in the diode string, and a gate terminal of the second transistor is coupled to a second reference voltage pin; and a third transistor, wherein a first terminal of the third transistor is coupled to a gate terminal of the first transistor, and a gate terminal of the third transistor is coupled to a second terminal of the second transistor, wherein, in response to a voltage at the first terminal of the second transistor being higher than a voltage at the gate terminal of the second transistor, the second transistor is configured to turn on the third transistor, and the third transistor is configured to transmit a voltage received from the first reference voltage pin to the gate terminal of the first transistor.

2 . The integrated circuit of claim 1 , further comprising:
at least one fourth transistor coupled in series with the first transistor between the I/O pad and the first reference voltage pin, wherein a gate terminal of the at least one fourth transistor is floating.

3 . The integrated circuit of claim 2 , wherein the at least one fourth transistor further comprises a number N of a plurality of fourth transistors stacked in a cascade connection, and n is a positive integer.

4 . The integrated circuit of claim 1 , further comprising:
a fourth transistor, wherein a first terminal of the fourth transistor is coupled to the second terminal of the second transistor, a gate terminal of the fourth transistor is coupled to the second reference voltage pin, and a second terminal of the fourth transistor is coupled to the first reference voltage pin; and a fifth transistor, wherein a first terminal of the fifth transistor is coupled to the second reference voltage pin, a gate terminal of the fifth transistor is coupled to the second terminal of the second transistor, and a second terminal of the fifth transistor is coupled to the gate terminal of the first transistor.

5 . The integrated circuit of claim 4 , wherein
in response to the voltage at the gate terminal of the second transistor being higher than the voltage at the first terminal of the second transistor, the fourth transistor is configured to transmit the voltage received from the first reference voltage pin to the gate terminal of the fifth transistor, and the fifth transistor is configured to be turned on to transmit the voltage received from the second reference voltage pin to the gate terminal of the first transistor.

6 . The integrated circuit of claim 1 , further comprising:
a fourth transistor, wherein a first terminal of the fourth transistor is coupled to the second terminal of the second transistor, a gate terminal of the fourth transistor is coupled to the second reference voltage pin, and a second terminal of the fourth transistor is coupled to the first reference voltage pin; a fifth transistor, wherein a first terminal of the fifth transistor is coupled to the second reference voltage pin, and a gate terminal of the fifth transistor is coupled to the second terminal of the second transistor; a sixth transistor, wherein a first terminal of the sixth transistor is coupled to a second terminal of the fifth transistor, a gate terminal of the sixth transistor is coupled to the second terminal of the second transistor, and a second terminal of the sixth transistor is coupled to the gate terminal of the first transistor; and a seventh transistor, wherein a first terminal of the seventh transistor is coupled to the second terminal of the third transistor, a gate terminal of the seventh transistor is coupled to the second reference voltage pin, and a second terminal of the seventh transistor is coupled to the first reference voltage pin.

7 . The integrated circuit of claim 6 , wherein
in response to that no ESD event occurs on the I/O pad, the fourth transistor, the fifth transistor and the sixth transistor are turned on to connect the second reference voltage pin with the gate terminal of the first transistor.

8 . The integrated circuit of claim 6 , further comprising:
an eighth transistor, wherein a first terminal of the eighth transistor is coupled to the second reference voltage pin, a second terminal of the eighth transistor is coupled to the gate terminal of the first transistor, and a gate terminal of the eighth transistor is coupled to the first reference voltage pin; a ninth transistor, wherein a first terminal of the ninth transistor is coupled to the gate terminal of the first transistor, a second terminal of the ninth transistor is coupled to the first reference voltage pin, and a gate terminal of the ninth transistor is coupled to the second terminal of the second transistor; and a power clamp coupled between the second reference voltage pin and the first reference voltage pin, wherein, in response to that an ESD event occurs from the I/O pad toward the second reference voltage pin, the eighth transistor is turned on to connect the second reference voltage pin with the gate terminal of the first transistor.

9 . The integrated circuit of claim 6 , further comprising:
a power clamp coupled between a third reference voltage pin and the first reference voltage pin, wherein, in response to that an ESD event occurs from the I/O pad toward the third reference voltage pin, the power clamp is configured to guide an ESD current induced by the ESD event from the first reference voltage pin to the third reference voltage pin.

10 . A method, comprising:
in response to a comparison between a first voltage at a first reference voltage pin and a second voltage at a first node coupled between an I/O pad and a second reference voltage pin, selectively transmitting the second voltage or a third voltage at the second reference voltage pin to gates of a first transistor and a second transistor that are coupled between the first reference voltage pin and the second reference voltage pin; controlling, in response to the second voltage or the third voltage that is transmitted, the first transistor or the second transistor to transmit the first voltage or the third voltage to an electrostatic discharge (ESD) primary circuit; and guiding, by the ESD primary circuit, an ESD current from the I/O pad to the second reference voltage pin.

11 . The method of claim 10 , wherein controlling the first transistor or the second transistor comprises:
transmitting, by the second transistor, the third voltage to the ESD primary circuit in response to the second voltage.

12 . The method of claim 10 , wherein controlling the first transistor or the second transistor comprises:
transmitting, by the first transistor, the first voltage to the ESD primary circuit in response to the third voltage.

13 . The method of claim 10 , further comprising:
transmitting the first voltage to a gate of a third transistor that is coupled between the second transistor and the second reference voltage pin; and in response to that an ESD event occurs from the I/O pad toward a third reference voltage pin, controlling the third transistor and the second transistor to transmit a third voltage at the third reference voltage pin to the ESD primary circuit.

14 . The method of claim 10 , further comprising:
transmitting the first voltage to a first terminal of a

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Peng Po-Lin
• Su Yu-Ti

Classifications

• H10D89/814

  involving a parasitic bipolar transistor triggered by the electrical biasing of the gate electrode of the FET, e.g. gate coupled transistors · CPC title

• H10D89/611 Primary

  using diodes as protective elements · CPC title

• H10D89/819 Primary

  Bias arrangements for gate electrodes of FETs, e.g. RC networks or voltage partitioning circuits (FETs in a Darlington configuration H10D89/817) · CPC title

• H10D89/931

  characterised by the dispositions of the protective arrangements · CPC title

• H10D89/711

  using bipolar transistors as protective elements · CPC title