Integrated circuit with electrostatic discharge protection

Patent metadata

Field	Value
Publication number	US-11289472-B2
Application number	US-202016943882-A
Country	US
Kind code	B2
Filing date	Jul 30, 2020
Priority date	Jul 30, 2020
Publication date	Mar 29, 2022
Grant date	Mar 29, 2022

Abstract

An integrated circuit includes an input/output (I/O) pad, an electrostatic discharge (ESD) primary circuit and a bias voltage generator. The electrostatic discharge primary circuit includes a first transistor. A first terminal of the first transistor is coupled to the I/O pad. The bias voltage generator is configured to provide a gate bias signal to the gate terminal of the first transistor. The bias voltage generator provides the gate bias signal at a first voltage level in response to that an ESD event occurs on the I/O pad. The bias voltage generator provides the gate bias signal at a second voltage level in response to that no ESD event occurs on the I/O pad. The first voltage level is lower than the second voltage level.

First claim

What is claimed is:

1. An integrated circuit, comprising:
an input/output (I/O) pad;
an electrostatic discharge (ESD) primary circuit comprising a first transistor, wherein a first terminal of the first transistor is coupled to the I/O pad; and
a bias voltage generator configured to provide a gate bias signal to a gate terminal of the first transistor, wherein the bias voltage generator provides the gate bias signal at a first voltage level in response to that an ESD event occurs on the I/O pad, and the bias voltage generator provides the gate bias signal at a second voltage level in response to that no ESD event occurs on the I/O pad, the first voltage level is lower than the second voltage level.

2. The integrated circuit of claim 1 , wherein a second terminal of the first transistor is coupled to a first reference voltage pin, in response to that the ESD event occurs on the I/O pad, a voltage level on the I/O pad exceeds a threshold voltage of the ESD primary circuit, and the ESD primary circuit is activated to guide an ESD current from the I/O pad through the ESD primary circuit to the first reference voltage pin.

3. The integrated circuit of claim 2 , wherein the ESD primary circuit further comprises a second transistor, a first terminal of the second transistor is coupled to the second terminal of the first transistor, a second terminal of the second transistor is coupled to the first reference voltage pin, a gate terminal of the second transistor is coupled to the first reference voltage pin or floating.

4. The integrated circuit of claim 1 , wherein the ESD primary circuit comprises cascade stacked transistors, the first transistor is a top one of the cascade stacked transistors.

5. The integrated circuit of claim 1 , wherein the bias voltage generator comprises:
a diode string comprising a plurality of cascade stacked diodes, wherein the cascade stacked diodes are coupled between the I/O pad and a first reference voltage pin;
a third transistor of a first conductivity type, wherein a first terminal of the third transistor is coupled to a first node between two of the cascade stacked diodes, a second terminal of the third transistor is coupled to a second node, a gate terminal of the third transistor is coupled to a second reference voltage pin;
a fourth transistor of a second conductivity type, wherein a first terminal of the fourth transistor is coupled to the second node, a second terminal of the fourth transistor is coupled to the first reference voltage pin, a gate terminal of the fourth transistor is coupled to the second reference voltage pin;
a fifth transistor of the first conductivity type, wherein a first terminal of the fifth transistor is coupled to the second reference voltage pin, a second terminal of the fifth transistor is coupled to the gate terminal of the first transistor, a gate terminal of the fifth transistor is coupled to the second node; and
a sixth transistor of the second conductivity type, wherein a first terminal of the sixth transistor is coupled to the second terminal of the fifth transistor and the gate terminal of the first transistor, a second terminal of the sixth transistor is coupled to the first reference voltage pin, a gate terminal of the sixth transistor is coupled to the second node.

6. The integrated circuit of claim 5 , wherein:
in response to that the ESD event occurs on the I/O pad, the third transistor and the sixth transistor are turned on to connect the first reference voltage pin with the gate terminal of the first transistor for providing the gate bias signal at the first voltage level, and
in response to that no ESD event occurs on the I/O pad, the fourth transistor and the fifth transistor are turned on to connect the second reference voltage pin with the gate terminal of the first transistor for providing the gate bias signal at the second voltage level.

7. The integrated circuit of claim 1 , further comprising:
an ESD secondary circuit, wherein the ESD secondary circuit comprises a diode string formed by a plurality of cascade stacked diodes, wherein the cascade stacked diodes are coupled between the I/O pad and a first reference voltage pin,
wherein the bias voltage generator comprises:
a third transistor of a first conductivity type, wherein a first terminal of the third transistor is coupled to a first node between two of the cascade stacked diodes, a second terminal of the third transistor is coupled to a second node, a gate terminal of the third transistor is coupled to a second reference voltage pin;
a fourth transistor of a second conductivity type, wherein a first terminal of the fourth transistor is coupled to the second node, a second terminal of the fourth transistor is coupled to the first reference voltage pin, a gate terminal of the fourth transistor is coupled to the second reference voltage pin;
a fifth transistor of the first conductivity type, wherein a first terminal of the fifth transistor is coupled to the second reference voltage pin, a second terminal of the fifth transistor is coupled to the gate terminal of the first transistor, a gate terminal of the fifth transistor is coupled to the second node; and
a sixth transistor of the second conductivity type, wherein a first terminal of the sixth transistor is coupled to the second terminal of the fifth transistor and the gate terminal of the first transistor, a second terminal of the sixth transistor is coupled to the first reference voltage pin, a gate terminal of the sixth transistor is coupled to the second node.

8. The integrated circuit of claim 7 , wherein:
in response to that the ESD event occurs on the I/O pad, the third transistor and the sixth transistor are turned on to connect the first reference voltage pin with the gate terminal of the first transistor for providing the gate bias signal at the first voltage level, and
in response to that no ESD event occurs on the I/O pad, the fourth transistor and the fifth transistor are turned on to connect the second reference voltage pin with the gate terminal of the first transistor for providing the gate bias signal at the second voltage level.

9. The integrated circuit of claim 1 , wherein the bias voltage generator comprises:
a diode string comprising a plurality of cascade stacked diodes, wherein the cascade stacked diodes are coupled between the I/O pad and a first reference voltage pin;
a third transistor of a first conductivity type, wherein a first terminal of the third transistor is coupled to a first node between two of the cascade stacked diodes, a second terminal of the third transistor is coupled to a second node, a gate terminal of the third transistor is coupled to a second reference voltage pin;
a fourth transistor of a second conductivity type, wherein a first terminal of the fourth transistor is coupled to the second node, a second terminal of the fourth transistor is coupled to the first reference voltage pin, a gate terminal of the fourth transistor is coupled to the second reference voltage pin;
a fifth transistor of the first conductivity type, wherein a first terminal of the fifth transistor is coupled to the second reference voltage pin, a gate terminal of the fifth transistor is coupled to the second node;
a sixth transistor of the first conductivity type, wherein a first terminal of the sixth transistor is coupled to the second terminal of the fifth transistor, a second terminal of the sixth transistor is coupled to the gate terminal of the first transistor, a gate terminal of the sixth transistor is coupled to the second node;
a seventh transistor of the second conductivity type, wherein a first terminal of the seventh transistor is coupled to the gate terminal of the first transistor, a gate terminal of th

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Peng Po-Lin
• Su Yu-Ti

Classifications

• H10D89/814

  involving a parasitic bipolar transistor triggered by the electrical biasing of the gate electrode of the FET, e.g. gate coupled transistors · CPC title

• H10D89/611 Primary

  using diodes as protective elements · CPC title

• H10D89/819 Primary

  Bias arrangements for gate electrodes of FETs, e.g. RC networks or voltage partitioning circuits (FETs in a Darlington configuration H10D89/817) · CPC title

• H10D89/931

  characterised by the dispositions of the protective arrangements · CPC title

• H10D89/711

  using bipolar transistors as protective elements · CPC title