Auto-referenced memory cell read techniques

Patent metadata

Field	Value
Publication number	US-2022208262-A1
Application number	US-202217697567-A
Country	US
Kind code	A1
Filing date	Mar 17, 2022
Priority date	Dec 22, 2017
Publication date	Jun 30, 2022
Grant date	—

Abstract

Methods, systems, and devices related to auto-referenced memory cell read techniques are described. The auto-referenced read may encode user data to include a predetermined number of bits having a first logic state prior to storing the user data in memory cells. The auto-referenced read may store a total number of bits of the user data having a first logic state in a separate set of memory cells. Subsequently, reading the user data may be carried out by applying a read voltage to the memory cells storing the user data while monitoring a series of switching events by activating a subset of the memory cells having the first logic state. During the read operation, the auto-referenced read may compare the number of activated memory cells to either the predetermined number or the total number to determine whether all the bits having the first logic state has been detected. When the number of activated memory cells matches either the predetermined number or the total number, the auto-referenced read may determine that the memory cells that have been activated correspond to the first logic state.

First claim

What is claimed is:

1 . A method, comprising:
apply a read voltage to a set of memory cells; update a value of a counter based on at least in part on a group of memory cells within the set of memory cells being activated based at least in part on the read voltage being applied; perform, after updating the value of the counter, a comparison of the value of the counter to a threshold; and read the set of memory cells based at least in part on the comparison.

2 . The method of claim 1 , further comprising:
determining, based at least in part on the comparison, that the value of the counter satisfies the threshold; and stopping application of the read voltage to the set of memory cells based at least in part on determining that the value of the counter satisfies the threshold.

3 . The method of claim 1 , further comprising:
determining, based at least in part on the comparison, that the value of the counter does not satisfy the threshold; continuing to apply the read voltage to the set of memory cells based at least in part on determining that the value of the counter does not satisfy the threshold; further updating the value of the counter based on at least in part on a second group of memory cells within the set of memory cells being activated based at least in part on the read voltage continuing to be applied; performing, after further updating the value of the counter, a second comparison of the value of the counter to the threshold; reading the set of memory cells based at least in part on the second comparison.

4 . The method of claim 1 , wherein a magnitude of the read voltage increases during a duration in which the read voltage is applied.

5 . The method of claim 4 , wherein the magnitude of the read voltage increases at a constant rate during at least a portion of the duration in which the read voltage is applied.

6 . The method of claim 4 , wherein the magnitude of the read voltage is constant at a first magnitude during a first portion of the duration for which the read voltage is applied and is constant at a second magnitude during a second portion of the duration for which the read voltage is applied, the second magnitude greater than the first magnitude.

7 . The method of claim 1 , further comprising:
applying the read voltage to a second set of memory cells storing an indication of the threshold; and determining the threshold based at least in part on applying the read voltage to the second set of memory cells.

8 . The method of claim 1 , further comprising:
applying a second read voltage to a second set of memory cells, the second set of memory cells storing an indication of the threshold; and determining the threshold based at least in part on applying the second read voltage to the second set of memory cells.

9 . The method of claim 8 , wherein:
a magnitude of the read voltage increases at a first rate during at least a portion of a first duration in which the read voltage is applied; and a magnitude of the second read voltage increases at a second rate during at least a portion of a second duration in which the second read voltage is applied, the second rate different than the first rate.

10 . The method of claim 8 , wherein application of the read voltage to the set of memory cells begins after application of the second read voltage to the second set of memory cells begins.

11 . The method of claim 1 , wherein the set of memory cells comprises memory cells of a first type, the method further comprising:
reading an indication of the threshold from a second set of memory cells that comprises memory cells of a second type, the second type different than the first type.

12 . The method of claim 1 , further comprising:
reading an indication of the threshold from a register of a memory device that comprises the set of memory cells.

13 . The method of claim 1 , further comprising:
reading an indication of the threshold from a second set of memory cells, the second set of memory cells and the set of memory cells coupled with a common access line.

14 . The method of claim 1 , further comprising:
encoding user data to comprise a target quantity of bits of a first logic value, the target quantity of bits equal to the threshold; and writing the encoded user data to the set of memory cells.

15 . The method of claim 1 , wherein reading the set of memory cells based at least in part on the comparison comprises:
determining, based at least in part on the value of the counter satisfying the threshold, that each activated memory cell within the set of memory cells stores a first logic value and each non-activated memory cell within the set of memory cells stores a second logic value, the second logic value different than the first logic value.

16 . An apparatus, comprising:
a memory array; and a controller coupled with the memory array and configured to cause the apparatus to:
apply a read voltage to a set of memory cells;
update a value of a counter based on at least in part on a first group of memory cells within the set of memory cells being activated based at least in part on the read voltage being applied;
perform, after updating the value of the counter, a comparison of the value of the counter to a threshold, the comparison; and
read the set of memory cells based at least in part on the comparison.

17 . The apparatus of claim 16 , wherein the controller is further configured to cause the apparatus to:
increase a magnitude of the read voltage during a duration in which the read voltage is applied.

18 . The apparatus of claim 16 , wherein the controller is further configured to cause the apparatus to:
apply the read voltage to a second set of memory cells storing an indication of the threshold; and determine the threshold based at least in part on applying the read voltage to the second set of memory cells.

19 . The apparatus of claim 16 , wherein the controller is further configured to cause the apparatus to:
apply a second read voltage to a second set of memory cells, the second set of memory cells storing an indication of the threshold; and determine the threshold based at least in part on applying the second read voltage to the second set of memory cells.

20 . The apparatus of claim 16 , wherein the controller is further configured to cause the apparatus to:
read an indication of the threshold from a second set of memory cells that comprises memory cells of a second type different than a first type of memory cells included in the set of memory cells, from a register, or from a third set of memory cells sharing a common access line with the set of memory cells.

Assignees

• Micron Technology Inc

Inventors

• Mirichigni Graziano
• Amato Paolo
• Pio Federico
• Orlando Alessandro
• Sforzin Marco

Classifications

• G11C7/1006

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title

• G11C2213/76

  Array using an access device for each cell which being not a transistor and not a diode · CPC title

• G11C2213/71

  Three dimensional array · CPC title

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title

• G11C2213/72

  Array wherein the access device being a diode · CPC title