Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-2022173112-A1
Application number	US-202117406418-A
Country	US
Kind code	A1
Filing date	Aug 19, 2021
Priority date	Nov 30, 2020
Publication date	Jun 2, 2022
Grant date	—

Abstract

A semiconductor memory device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region, the boundary element isolation layer being in a boundary element isolation recess and including first and second boundary liner layers extending along a profile of the boundary element isolation recess and a first gate structure on the core region and at least a part of the boundary element isolation layer, wherein the first gate structure includes a first high dielectric layer, and a first gate insulating pattern below the first high dielectric layer, with a top surface of the substrate being a base reference level, the first gate insulating pattern does not overlap a top surface of the first boundary liner layer, and wherein the first gate insulating pattern includes a first_1 gate insulating pattern between a top surface of the second boundary liner layer and a bottom surface of the first high dielectric layer, and a first_2 gate insulating pattern disposed a top surface of the core region and a bottom surface of the first high dielectric layer.

First claim

What is claimed is:

1 . A semiconductor memory device comprising:
a substrate including a cell region, a core region, and a boundary region between the cell region and the core region; a boundary element isolation layer in the boundary region, the boundary element isolation layer being in a boundary element isolation recess and including first and second boundary liner layers extending along a profile of the boundary element isolation recess; and a first gate structure on the core region and at least a part of the boundary element isolation layer, wherein the first gate structure includes a first high dielectric layer, and a first gate insulating pattern below the first high dielectric layer, with a top surface of the substrate being a base reference level, the first gate insulating pattern does not overlap a top surface of the first boundary liner layer in a direction perpendicular to the top surface of the substrate, and wherein the first gate insulating pattern includes a first_1 gate insulating pattern between a top surface of the second boundary liner layer and a bottom surface of the first high dielectric layer, and a first_2 gate insulating pattern between a top surface of the core region and a bottom surface of the first high dielectric layer.

2 . The semiconductor memory device of claim 1 , wherein the boundary element isolation layer is on the second boundary liner layer and includes a boundary element isolation filling layer in the boundary element isolation recess, and
wherein the first gate insulating pattern does not overlap the boundary element isolation filling layer in the direction perpendicular to the top surface of the substrate.

3 . The semiconductor memory device of claim 2 , wherein the first high dielectric layer is in physical contact with the boundary element isolation filling layer.

4 . The semiconductor memory device of claim 1 , wherein the first high dielectric layer overlaps the boundary element isolation layer and the substrate of the core region in the direction perpendicular to the top surface of the substrate.

5 . The semiconductor memory device of claim 1 , wherein the first high dielectric layer is in physical contact with the first boundary liner layer.

6 . The semiconductor memory device of claim 1 , further comprising:
a core element isolation layer in the core region; and a second gate structure spaced apart from the core element isolation layer.

7 . The semiconductor memory device of claim 6 , wherein the second gate structure includes a second gate insulating pattern, a second high dielectric layer on the second gate insulating pattern, and a second work function metal pattern on the second high dielectric layer.

8 . The semiconductor memory device of claim 1 , further comprising:
a word line structure buried in the cell region; and a lower electrode on the cell region.

9 . A semiconductor memory device comprising:
a substrate including a cell region, a core region, and a boundary region between the cell region and the core region; a boundary element isolation layer in the boundary region; a first gate structure on the core region and at least a part of the boundary element isolation layer; a core element isolation layer in the core region, the core element isolation layer being in a core element isolation recess and including first and second core liner layers extending along a boundary of the core element isolation recess; and a second gate structure on the core region and at least a part of the core element isolation layer, wherein the first gate structure includes a first high dielectric layer and a first gate insulating pattern below the first high dielectric layer with a top surface of the substrate being a base reference level, wherein the second gate structure includes a second high dielectric layer and a second gate insulating pattern below the second high dielectric layer with the top surface of the substrate being the base reference level, and wherein the second gate insulating pattern does not overlap a top surface of the first core liner layer, and overlaps a top surface of the second core liner layer and a top surface of the core region in a direction perpendicular to the top surface of the substrate.

10 . The semiconductor memory device of claim 9 , wherein the first gate insulating pattern does not overlap a top surface of the first boundary liner layer, and overlaps a top surface of the second boundary liner layer and the top surface of the core region in the direction perpendicular to the top surface of the substrate.

11 . The semiconductor memory device of claim 9 , wherein the core element isolation layer is on the second core liner layer and includes a core element isolation filling layer in the core element isolation recess, and
wherein the second gate insulating pattern does not overlap the core element isolation filling layer in the direction perpendicular to the top surface of the substrate.

12 . The semiconductor memory device of claim 11 , wherein the second high dielectric layer is in physical contact with the core element isolation filling layer.

13 . The semiconductor memory device of claim 9 , wherein the second high dielectric layer overlaps the core element isolation layer and the top surface of the substrate of the core region in the direction perpendicular to the top surface of the substrate.

14 . The semiconductor memory device of claim 9 , wherein the second high dielectric layer is in physical contact with the first core liner layer.

15 . The semiconductor memory device of claim 9 , further comprising:
a word line structure buried in the cell region; and a lower electrode on the cell region.

16 . A semiconductor memory device comprising:
a substrate including a cell region, a core region, and a boundary region between the cell region and the core region; a boundary element isolation layer in the boundary region, the boundary element isolation layer being in a boundary element isolation recess and including first and second boundary liner layers extending along a boundary of the boundary element isolation recess; a first gate structure on the core region and at least a part of the boundary element isolation layer; and a second gate structure on the core region, wherein the first gate structure includes a first high dielectric layer and a first gate insulating pattern below the first high dielectric layer with a top surface of the substrate being a base reference level, wherein the second gate structure includes a channel layer containing silicon germanium and a second gate insulating pattern on the channel layer, wherein the first gate insulating pattern does not overlap a top surface of the first boundary liner layer, and overlaps a top surface of the second boundary liner layer and a top surface of the core region in a direction perpendicular to the top surface of the substrate, and wherein a thickness of the first gate insulation pattern is smaller than a thickness of the second gate insulation pattern.

17 . The semiconductor memory device of claim 16 , wherein the boundary element isolation layer is on the second boundary liner layer and includes a boundary element isolation filling layer in the boundary element isolation recess, and
wherein the first gate insulating pattern does not overlap the boundary element isolation filling layer in the direction perpendicular to the top surface of the substrate.

18 . The semiconductor memory device of claim 17 , wherein the first high dielectric layer is in phy

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Dong Oh
• Kil Gyu Hyun
• Han Jung Hoon
• Back Doo San

Classifications

• H01L27/10814

  Electricity · mapped topic

• H01L27/10897 Primary

  Electricity · mapped topic

• H01L27/10823

  Electricity · mapped topic

• H10B12/315 Primary

  with the capacitor higher than a bit line · CPC title

• H10B12/34 Primary

  the transistor being at least partially in a trench in the substrate · CPC title