Controlled wetting and spreading of metals on substrates using porous interlayers and related articles

Patent metadata

Field	Value
Publication number	US-2022167501-A1
Application number	US-202217668660-A
Country	US
Kind code	A1
Filing date	Feb 10, 2022
Priority date	Apr 17, 2018
Publication date	May 26, 2022
Grant date	—

Abstract

The disclosure generally relates to a method of creating patterned metallic circuits (e.g., silver circuits) on a substrate (e.g., a ceramic substrate). A porous metal interlayer (e.g., porous nickel) is applied to the substrate to improve wetting and adhesion of the patterned metal circuit material to the substrate. The substrate is heated to a temperature sufficient to melt the patterned metal circuit material but not the porous metal interlayer. Spreading of molten metal circuit material on the substrate is controlled by the porous metal interlayer, which can itself be patterned, such as having a defined circuit pattern. Thick-film silver or other metal circuits can be custom designed in complicated shapes for high temperature/high power applications. The materials designated for the circuit design allows for a low-cost method of generating silver circuits other metal circuits on a ceramic substrate.

First claim

1 .- 30 . (canceled)

31 . A patterned, wetted substrate:
(a) a substrate; (b) a bulk patterned second metal layer adjacent to the substrate, the bulk second metal layer comprising a second metal and optionally a first metal, the first metal being at a lower concentration than the second metal in the bulk patterned second metal layer when present; and (c) an interfacial layer between the bulk patterned second metal layer and the substrate, the interfacial layer comprising the first metal; wherein the second metal has a lower melting point than that of the first metal.

32 . The patterned, wetted substrate of claim 31 , further comprising one or more electronic components mounted to the to the pattern, wetted substrate in electrical connection to an element of the bulk patterned second metal layer;
wherein the bulk patterned second metal layer has a spatial pattern corresponding to electronic circuitry.

33 . The patterned, wetted substrate of claim 31 , wherein the bulk patterned second metal layer has a first metal concentration of 20 wt. % or less; and
the interfacial layer has a first metal concentration of at least 10 wt. % and greater than the first metal concentration of the bulk patterned second metal layer.

34 . The patterned, wetted substrate of claim 31 , wherein the bulk patterned second metal layer has a second metal concentration ranging from 70 wt. % to 99 wt. %.

35 . The patterned, wetted substrate of claim 31 , wherein the bulk patterned second metal layer is substantially free from discrete first metal particles having a size greater than 1 μm.

36 . The patterned, wetted substrate of claim 31 , wherein:
the first metal comprises at least one of nickel, aluminum, cobalt, iron, copper, titanium and combinations thereof; and the second metal comprises at least one of silver, aluminum, tin, bismuth, nickel, copper, gold, cobalt, and combinations thereof.

37 . The patterned, wetted substrate of claim 31 , wherein the second metal comprises silver.

38 . The patterned, wetted substrate of claim 31 , wherein: the substrate comprises a ceramic material.

39 . The patterned, wetted substrate of claim 38 , wherein the ceramic material is selected from the group consisting of aluminum oxide, aluminum nitride, gallium nitride, aluminum gallium nitride, beryllium oxide, zirconium oxide, cerium oxide, zinc oxide, silicon carbide, silicon nitride, tungsten carbide, doped derivatives thereof, and combinations thereof.

40 . The patterned, wetted substrate of claim 38 , wherein the ceramic material comprises one or more of aluminum oxide (alumina), aluminum nitride, gallium nitride, aluminum gallium nitride, aluminum gallium indium nitride, beryllium oxide, silicon carbide and silicon nitride.

41 . The patterned, wetted substrate of claim 38 , wherein the ceramic material comprises a stabilized zirconium oxide (zirconia).

42 . The patterned, wetted substrate of claim 38 , wherein the ceramic material comprises one or more of lanthanum strontrium manganite, lanthanum strontium cobaltite, and lanthanum strontium ferrite.

43 . The patterned, wetted substrate of claim 31 , wherein the substrate comprises one or more of a metal material and a semiconductor material.

44 . The patterned, wetted substrate of claim 31 , wherein the substrate comprises a stainless steel alloy.

45 . The patterned, wetted substrate of claim 31 , wherein the substrate comprises a nickel-based high temperature alloy.

46 . The patterned, wetted substrate of claim 31 , wherein the melting point of the second metal is lower than the melting point of the first metal by at least 300° C.

47 . The patterned, wetted substrate of claim 31 , wherein the melting point of the second metal is lower than the melting point of the first metal by 300° C. to 700° C.

48 . The patterned, wetted substrate of claim 31 , wherein the melting point of the second metal is lower than the melting point of the first metal by 700° C. to 1000° C.

Assignees

• Univ Michigan State

Inventors

• Nicholas Jason Dale
• Zhou Quan
• Bieler Thomas Rector

Classifications

• H05K3/1283 Primary

  After-treatment of the printed patterns, e.g. sintering or curing methods · CPC title

• H05K2203/1147

  Sealing or impregnating, e.g. of pores · CPC title

• H05K3/3478

  Application of solder preforms; Transferring prefabricated solder patterns · CPC title

• H05K1/0306 Primary

  Inorganic insulating substrates, e.g. ceramic, glass · CPC title

• H05K3/22

  Secondary treatment of printed circuits {(H05K3/1283 takes precedence; embedding circuits in grooves by pressure H05K3/107)} · CPC title