Apparatuses, systems, and methods for error correction

Patent metadata

Field	Value
Publication number	US-2022156148-A1
Application number	US-202217591362-A
Country	US
Kind code	A1
Filing date	Feb 2, 2022
Priority date	Dec 31, 2019
Publication date	May 19, 2022
Grant date	—

Abstract

Apparatuses, systems, and methods for error correction. A memory device may have a number of memory cells each of which stores a bit of information. One or more error correction code (ECC) may be used to determine if the bits of information contain any errors. To mitigate the effects of failures of adjacent memory cells, the information may be divided into a first group and a second group, where each group contains information from memory cells which are non-adjacent to other memory cells of that group. Each group of information may include data bits and parity bits used to correct those data bits. For example, as part of a read operation, a first ECC circuit may receive information from even numbered memory cells, while a second ECC circuit may receive information from odd numbered memory cells.

First claim

What is claimed is:

1 . A method comprising:
activating a word line of a memory as part of a read operation; receiving, with a first error correction code (ECC) circuit, a first set of data and a first set of parity bits from a first set of memory cells of the word line, wherein the first set of memory cells are non-adjacent to each other; and receiving, with a second error correction code (ECC) circuit, a second set of data and a second set of parity bits from a second set of memory cells of the word line, wherein the second set of memory cells are non-adjacent to each other.

2 . The method of claim 1 , further comprising:
providing the first set of data and the first set of parity bits along odd digit lines and odd main input/output lines to the first ECC circuit; and providing the second set of data and the second set of parity bits along even digit and even main input/output lines to the second ECC circuit.

3 . The method of claim 1 , further comprising activating a plurality of memory cells along the word line as part of the read operation, wherein the first set of memory cells are odd ones of the plurality of memory cells and the second set of memory cells are of even ones of the plurality of memory cells.

4 . The method of claim 1 , further comprising activating a first portion of the word line on a first side of a row decoder and a second portion of the word line on a second side of the row decoder as part of the read operation.

5 . The method of claim 1 , further comprising:
locating and correcting errors in the first set of data based on the first set of parity bits with the first ECC circuit; and locating and correcting errors in the second set of data based on the second set of parity bits with the second ECC circuit.

6 . The method of claim 5 , further comprising correcting a first error in the first set of data wherein the first error was stored in a first memory cell of the first set of memory cells;
correcting a second error in the second set of data wherein the second error was stored in a second memory cell of the second set of memory cells, wherein the first memory cell is adjacent to the second memory cell.

7 . The method of claim 1 , further comprising:
generating the first set of parity bits based on the first set of data bits and writing the first set of data bits and the first set of parity bits to the first set of memory cells as part of a write operation; and generating the second set of parity bits based on the second set of data bits and writing the second set of data bits and the second set of parity bits to the second set of memory cells as part of a write operation.

8 . An apparatus comprising
a word line comprising a first plurality of memory cells and a second plurality of memory cells, wherein none of the first plurality of memory cells are adjacent to others of the first plurality of memory cells and none of the second plurality of memory cells are adjacent to others of the second plurality of memory cells; a first error correction code (ECC) circuit configured to receive a first set of data and a first set of parity bits from the first plurality of memory cells as part of a read operation; and a second ECC circuit configured to receive a second set of data and a second set of parity bits from the second plurality of memory cells as part of the read operation.

9 . The apparatus of claim 8 , wherein the word line is coupled to a plurality of memory cells which includes the first and the second plurality of memory cells, and wherein the first plurality of memory cells are odd ones of the plurality of memory cells and the second plurality of memory cells are even ones of the plurality of memory cells.

10 . The apparatus of claim 8 , further comprising:
a plurality of odd digit lines and odd main input/output lines configured to couple the first plurality of memory cells to the first ECC circuit; and a plurality of even digit lines and even main input/output lines configured to couple the second plurality of memory cells to the second ECC circuit.

11 . The apparatus of claim 8 , wherein the first ECC circuit is configured to locate and correct errors in the first set of data based on the first set of parity bits, and wherein the second ECC circuit is configured to locate and correct errors in the second set of data based on the second set of parity bits.

12 . The apparatus of claim 11 , wherein the first set of data includes a first error stored in a first memory cell of the first plurality of memory cells, wherein the second set of data includes a second error located in a second memory cell of the second plurality of memory cells, wherein the first ECC circuit is configured to correct the first error, wherein the second ECC circuit is configured to correct the second error, and wherein the first memory cell is adjacent to the second memory cell.

13 . The apparatus of claim 8 , wherein each of the first plurality of memory cells is adjacent to at least one of the second plurality of memory cells, and each of the second plurality of memory cells is adjacent to at least one of the first plurality of memory cells.

14 . The apparatus of claim 8 , wherein the first word line has a first portion which extends from a first side of a row decoder and a second portion which extends from a second side of the row decoder.

15 . An apparatus comprising:
a word line comprising a plurality of memory cells at the intersections of a plurality of digit lines; a first error correction code (ECC) circuit coupled to odd ones of the plurality of digit lines and configured to receive a first set of data and a first set of parity bits along the odd ones of the plurality of digit lines as part of a read operation; and a second ECC circuit coupled to even ones of the plurality of digit lines and configured to receive a second set of data and a second set of parity bits along the even ones of the plurality of digit lines as part of the read operation.

16 . The apparatus of claim 15 , wherein the first ECC circuit is not coupled to the even ones of the plurality of digit lines and the second ECC circuit is not coupled to the odd ones of the plurality of digit lines.

17 . The apparatus of claim 15 , wherein the odd ones of the plurality of digit lines are coupled to a first set of the plurality of memory cells, wherein the even ones of the plurality of digit lines are coupled to a second set of the plurality of memory cells, and wherein memory cells of the first set of the plurality of memory cells are not adjacent to others of the first set of the plurality of memory cells and wherein memory cells of the second set of the plurality of memory cells are not adjacent to others of the second set of the plurality of memory cells.

18 . The apparatus of claim 15 , wherein the first ECC circuit is configured to locate and correct errors in the first set of data based on the first set of parity bits and wherein the second ECC circuit is configured to locate and correct errors in the second set of data based on the second set of parity bits.

19 . The apparatus of claim 15 , further comprising:
a first plurality of main input/output lines configured to couple the odd ones of the plurality of digit lines to the first ECC circuit; and a second plurality of main input/output lines configured to couple the even ones of the plurality of digit lines to the second ECC circuit.

20 . The apparatus of claim 15 , further comprising a plurality of sense amplifiers, wherein the

Assignees

• Micron Technology Inc

Inventors

• Fujiwara Yoshinori
• Kotti Vivek
• Wieduwilt Christopher G
• Johnson Jason M
• Werhane Kevin G

Classifications

• G06F11/1048 Primary

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G11C11/4097 Primary

  Bit-line organisation, e.g. bit-line layout, folded bit lines · CPC title

• G06F11/1032

  Simple parity · CPC title

• G06F11/1044

  with specific ECC/EDC distribution · CPC title

• G11C11/4091

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title