Image sensor

Patent metadata

Field	Value
Publication number	US-2022149101-A1
Application number	US-202117377792-A
Country	US
Kind code	A1
Filing date	Jul 16, 2021
Priority date	Nov 11, 2020
Publication date	May 12, 2022
Grant date	—

Abstract

An image sensor includes a first chip including a pixel region, a pad region, and an optical black region interposed between the pixel region and the pad region, and a second chip being in contact with a first surface of the first chip and including circuits for driving the first chip. The first chip includes a first substrate, a device isolation portion disposed in the first substrate and defining unit pixels, an interlayer insulating layer interposed between the first substrate and the second chip, a connection wiring structure disposed in the interlayer insulating layer, and a connection contact plug disposed in the interlayer insulating layer and connecting the connection wiring structure to the device isolation portion in the optical black region. The image sensor further includes a conductive pad disposed in the first chip or the second chip.

First claim

What is claimed is:

1 . An image sensor comprising:
a first chip comprising a pixel region, a pad region, and an optical black region interposed between the pixel region and the pad region; and a second chip being in contact with a first surface of the first chip and comprising circuits for driving the first chip, wherein the first chip comprises:
a first substrate;
a device isolation portion disposed in the first substrate and defining unit pixels;
an interlayer insulating layer interposed between the first substrate and the second chip;
a connection wiring structure disposed in the interlayer insulating layer; and
a connection contact plug disposed in the interlayer insulating layer and connecting the connection wiring structure to the device isolation portion in the optical black region, and
wherein the image sensor further comprises a conductive pad disposed in the first chip or the second chip and being exposed in the pad region by a recess region penetrating the first substrate and the interlayer insulating layer, the conductive pad being electrically connected to the device isolation portion through the connection wiring structure and the connection contact plug.

2 . The image sensor of claim 1 , wherein the conductive pad is disposed in the interlayer insulating layer of the first chip and is interposed between the connection wiring structure and the second chip.

3 . The image sensor of claim 1 , wherein the first chip further comprises:
transistors disposed on the first substrate in the pixel region; and first contact plugs connected to the transistors, and wherein the connection contact plug is disposed at substantially a same level as the first contact plugs.

4 . The image sensor of claim 3 , wherein a bottom surface of the connection contact plug is disposed at substantially a same height as bottom surfaces of the first contact plugs.

5 . The image sensor of claim 1 , wherein the connection wiring structure is disposed in the optical black region, and
wherein the connection contact plug comprises a plurality of connection contact plugs connected in common to the connection wiring structure.

6 . The image sensor of claim 5 , wherein the connection wiring structure has a ring shape surrounding the pixel region in a plan view.

7 . The image sensor of claim 1 , wherein the device isolation portion comprises:
a conductive pattern; and an isolation insulating layer surrounding a sidewall of the conductive pattern, wherein the connection contact plug comprises:
an upper portion connected to the conductive pattern; and
a lower portion connected to the connection wiring structure, and
wherein a width of the lower portion of the connection contact plug is greater than a width of the upper portion of the connection contact plug.

8 . The image sensor of claim 1 , wherein the first chip further comprises an optical black pattern disposed on a second surface of the first chip, the second surface being opposite to the first surface, and
wherein the connection contact plug overlaps with the optical black pattern.

9 . The image sensor of claim 1 , wherein the first chip further comprises upper connection pads interposed between the conductive pad and the second chip, and
wherein the second chip further comprises lower connection pads connected directly to the upper connection pads.

10 . The image sensor of claim 9 , wherein any one or any combination of the upper connection pads is connected to a bottom surface of the conductive pad through a via.

11 . The image sensor of claim 9 , wherein the upper connection pads and the lower connection pads comprise a same metal material, and
wherein the conductive pad comprises a metal material different from the metal material of the upper connection pads and the lower connection pads.

12 . The image sensor of claim 11 , wherein the upper connection pads and the lower connection pads comprise copper, and
wherein the conductive pad comprises aluminum.

13 . The image sensor of claim 1 , wherein the device isolation portion comprises:
a deep device isolation portion extending from a first surface of the first substrate toward a second surface of the first substrate, the second surface being opposite to the first surface; and a back device isolation portion extending from the second surface of the first substrate to the deep device isolation portion and defining the unit pixels along with the deep device isolation portion.

14 . The image sensor of claim 1 , wherein the first chip further comprises a pad contact plug connecting the connection wiring structure to the conductive pad.

15 . The image sensor of claim 1 , wherein the first chip further comprises metal patterns disposed in the pixel region, and
wherein the metal patterns are disposed at substantially a same level as the conductive pad.

16 . An image sensor comprising:
a first chip comprising a pixel region, a pad region, and an optical black region interposed between the pixel region and the pad region; and a second chip being in contact with a first surface of the first chip and comprising circuits for driving the first chip, wherein the first chip comprises:
a first substrate;
a device isolation portion disposed in the first substrate and defining unit pixels;
an interlayer insulating layer interposed between the first substrate and the second chip;
a connection wiring structure disposed in the interlayer insulating layer of the optical black region and having a ring shape surrounding the pixel region in a plan view;
connection contact plugs disposed in the interlayer insulating layer and connecting the connection wiring structure to the device isolation portion in the optical black region; and
a conductive pad disposed in the interlayer insulating layer and being exposed in the pad region by a recess region penetrating the first substrate, the conductive pad being electrically connected to the device isolation portion through the connection wiring structure and the connection contact plugs, and
wherein the connection contact plugs are connected in common to the conductive pad.

17 . The image sensor of claim 16 , wherein the conductive pad is interposed between the connection wiring structure and the second chip.

18 . The image sensor of claim 16 , wherein the first chip further comprises:
transistors disposed on the first substrate in the pixel region; and first contact plugs connected to the transistors, and wherein bottom surfaces of the connection contact plugs are disposed at substantially a same height as bottom surfaces of the first contact plugs.

19 . An image sensor comprising:
a first chip comprising a pixel region, a pad region, and an optical black region interposed between the pixel region and the pad region; and a second chip being in contact with a first surface of the first chip and comprising circuits for driving the first chip, wherein the first chip comprises:
a first substrate;
a device isolation portion disposed in the first substrate and defining unit pixels;
photoelectric conversion portions disposed in the first substrate in the unit pixels, respectively;
transfer gates disposed on the first substrate;
an upper interlayer insulating layer interposed between the first substrate and the second chip;
first wiring lines disposed in the upper interlayer insulating layer and comprising at least one connection wiring line constituting a connection wiring structure in the optical black region;
a connection contac

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Dong-Chul
• Lee Beomsuk
• Jang Minho
• Cho Kwansik

Classifications

• H10F39/807 Primary

  Pixel isolation structures · CPC title

• H10F39/809

  of hybrid image sensors · CPC title

• H10F39/8057 Primary

  Optical shielding · CPC title

• H10F39/8037

  the integrated elements comprising a transistor · CPC title

• H10F39/8033

  Photosensitive area · CPC title