Electronic circuit adjusting timing of clock based on bits of output data from sub-ranging analog-to-digital converter

Patent metadata

Field	Value
Publication number	US-2019222220-A1
Application number	US-201816194824-A
Country	US
Kind code	A1
Filing date	Nov 19, 2018
Priority date	Jan 15, 2018
Publication date	Jul 18, 2019
Grant date	—

Abstract

An electronic circuit includes a reference ADC, a delay circuit, and a main ADC. The reference ADC converts an input signal to an upper bit string of output data, in response to a reference clock. The delay circuit delays a source clock by a delay time to output a main clock. The main ADC converts the input signal to a lower bit string of the output data, in response to the main clock. When a value of the most significant bit included in the lower bit string is identical to a value of the bit which is adjacent to the most significant bit and lower than the most significant bit, the delay time is adjusted based on a direction in which a level of the input signal is changed and the value of the most significant bit of the lower bit string.

First claim

What is claimed is:

1 . An electronic circuit comprising:
a reference analog-to-digital converter (ADC) to convert an input signal to a first bit string of output data, in response to a reference clock; a delay circuit to delay a source clock by a delay time to output a main clock; and a main ADC to convert the input signal to a second bit string of the output data, in response to the main clock, wherein when a value of a first bit included in the second bit string is identical to a value of a second bit included in the second bit string, the delay time is adjusted based on a direction in which a level of the input signal is changed and the value of the first bit.

2 . The electronic circuit of claim 1 , wherein
the first bit string comprises upper bits of the output data, and the second bit string comprises lower bits other than the upper bits of the output data.

3 . The electronic circuit of claim 1 , wherein
the first bit comprises a most significant bit of the second bit string, and the second bit comprises a bit that is adjacent to the most significant bit of the second bit string and is lower than the most significant bit.

4 . The electronic circuit of claim 1 , wherein
the output data is generated corresponding to first timings associated with the reference clock and the main clock, and the direction in which the level of the input signal is changed is obtained based on a difference between following output data and preceding output data, the following output data being generated corresponding to second timings immediately after the first timings, the preceding output data being generated corresponding to third timings immediately before the first timings.

5 . The electronic circuit of claim 1 , wherein
when a timing of the reference clock is different from a timing of the main clock, the value of the first bit is identical to the value of the second bit.

6 . The electronic circuit of claim 1 , wherein as the delay time increases or decreases, timings of the main clock are delayed or advanced.

7 . The electronic circuit of claim 1 , wherein
when the first bit has a first logic value and the level of the input signal increases, timings of the main clock are delayed as the delay time is adjusted, and when the first bit has a second logic value and the level of the input signal increases, the timings of the main clock are advanced as the delay time is adjusted.

8 . The electronic circuit of claim 1 , wherein
when the first bit has a first logic value and the level of the input signal decreases, timings of the main clock are advanced as the delay time is adjusted, and when the first bit has a second logic value and the level of the input signal decreases, the timings of the main clock are delayed as the delay time is adjusted.

9 . The electronic circuit of claim 1 , wherein
the output data is generated corresponding to first timings associated with the reference clock and the main clock, and the electronic circuit further comprises:
a slope calculator to output a slope value indicating the direction in which the level of the input signal is changed, based on a difference between following output data and preceding output data, the following output data being generated corresponding to second timings immediately after the first timings, preceding output data being generated corresponding to third timings immediately before the first timings; and
a delay calibrator to output a delay calibration value based on the value of the first bit and the slope value, such that the delay time is adjusted.

10 . The electronic circuit of claim 9 , wherein
when the first bit has a first logic value and the slope value has the first logic value, the delay time increases based on the delay calibration value, when the first bit has a second logic value and the slope value has the first logic value, the delay time decreases based on the delay calibration value, and when the first bit has the first logic value and the slope value has the second logic value, the delay time decreases based on the delay calibration value.

11 . The electronic circuit of claim 9 , further comprising an accumulator to accumulate delay calibration values output from the delay calibrator, to output a final calibration value, wherein
the delay time increases or decreases based on the final calibration value.

12 . The electronic circuit of claim 11 , wherein
the accumulator is to accumulate the delay calibration values output from the delay calibrator, for a reference time duration or until a reference number of delay calibration values are accumulated.

13 . The electronic circuit of claim 9 , further comprising a timing error detector to output a detection value indicating that a timing of the reference clock is different from a timing of the main clock, based on the first bit and the second bit, wherein
the slope calculator and the delay calibrator are to be activated in response to the detection value, and to be deactivated when the detection value is not output.

14 . The electronic circuit of claim 1 , wherein
as the delay time is adjusted, a timing of the main clock is adjusted to be identical to a timing of the reference clock.

15 . An electronic circuit comprising:
a reference analog-to-digital converter (ADC) to convert an input signal to first bit strings of a plurality of output data, in response to a reference clock; a plurality of delay circuits to delay a source clock by different delay times to output a plurality of main clocks providing different timings; and a plurality of main ADCs to convert the input signal to second bit strings of the plurality of output data, in response to the plurality of main clocks, wherein when a value of a first bit included in one second bit string among the second bit strings is identical to a value of a second bit included in the one second bit string, a timing of a main clock, among the plurality of main clocks, associated with output data, among the plurality of output data, corresponding to the one second bit string is adjusted based on a direction in which a level of the input signal is changed and the value of the first bit.

16 . The electronic circuit of claim 15 , wherein
the plurality of main clocks is time-interleaved such that the input signal is sampled successively at each of the different timings, and a timing of the reference clock corresponds to a timing of a different main clock for each cycle of the reference clock.

17 . The electronic circuit of claim 15 , wherein
the different delay times of the plurality of delay circuits are adjusted such that the different timings of the plurality of main clocks are adjusted, and the different delay times of the plurality of delay circuits are independently adjusted based on the direction in which the level of the input signal is changed and values of first bits respectively included in the second bit strings.

18 . An electronic circuit comprising:
a plurality of auxiliary analog-to-digital converters (ADC) to convert an input signal to first bit strings of a plurality of output data, in response to a plurality of auxiliary clocks providing different first timings; and a plurality of main ADCs to convert the input signal to second bit strings of the plurality of output data, in response to a plurality of main clocks providing different second timings, wherein when a value of a first bit included in one second bit string among the second bit strings is identical to a value of a second bit included in the one

Assignees

• Korea Advanced Inst Sci & Tech

Inventors

• Ryu Seung-Tak
• Chang Dongjin

Classifications

• H03M1/14 Primary

  Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit · CPC title

• H03M1/0836

  of phase error, e.g. jitter · CPC title

• H03M1/0624

  by synchronisation · CPC title

• H03M1/1215

  using time-division multiplexing · CPC title

• H03M1/10

  Calibration or testing · CPC title