Ion beam etching with sidewall cleaning

Patent metadata

Field	Value
Publication number	US-2022131071-A1
Application number	US-202017432059-A
Country	US
Kind code	A1
Filing date	Feb 26, 2020
Priority date	Feb 28, 2019
Publication date	Apr 28, 2022
Grant date	—

Abstract

Patterned magnetoresistive random access memory (MRAM) stacks are formed by performing a main etch through a plurality of MRAM layers disposed on a substrate, where the main etch includes using ion beam etching (IBE). After the main etch, gapfill dielectric material is deposited in spaces between the patterned MRAM stacks, and the gapfill dielectric material is selectively etched or otherwise formed to an etch depth that is above a depth of an underlayer. After the gapfill dielectric material is formed, at least some of the gapfill dielectric material and any electrically conductive materials deposited on sidewalls of the patterned MRAM stacks are removed by performing an IBE trim etch.

First claim

1 . An ion beam etching method, the method comprising:
etching through a plurality of magnetoresistive random access memory (MRAM) layers disposed on a substrate to form patterned MRAM stacks, wherein the plurality of MRAM layers include one or more magnetic layers and a tunnel barrier layer, wherein etching through the plurality of MRAM layers includes ion beam etching (IBE) through at least the tunnel barrier layer; forming a gapfill dielectric material in spaces between the patterned MRAM stacks; and performing an IBE trim etch to remove at least some of the gapfill dielectric material and electrically conductive materials deposited on sidewalls of the patterned MRAM stacks.

2 . The method of claim 1 , wherein the gapfill dielectric material is formed to a sufficient depth above an underlayer disposed between the substrate and the plurality of MRAM layers so that performing the IBE trim etch does not cause recess into the underlayer.

3 . The method of claim 2 , wherein the sufficient depth above the underlayer is between about 1 nm and about 20 nm above a top surface of the underlayer.

4 . The method of claim 1 , wherein forming the gapfill dielectric material in spaces between the patterned MRAM stacks comprises:
depositing the gapfill dielectric material in the spaces between the patterned MRAM stacks and over the patterned MRAM stacks.

5 . The method of claim 4 , wherein forming the gapfill dielectric material in spaces between the patterned MRAM stacks further comprises:
selectively etching the gapfill dielectric material to an etch depth above the depth of the tunnel barrier layer.

6 . The method of claim 5 , further comprising:
planarizing the gapfill dielectric material deposited over the patterned MRAM stacks.

7 . The method of claim 1 , wherein the gapfill dielectric material includes silicon nitride, silicon oxide, silicon oxycarbide, germanium oxide, magnesium oxide, germanium nitride, or combinations thereof.

8 . The method of claim 7 , wherein the gapfill dielectric material includes one or both of silicon nitride and silicon oxide.

9 . The method of claim 1 , wherein operations of etching through the plurality of MRAM layers, forming the gapfill dielectric material, and performing the IBE trim etch are performed without introducing a vacuum break in between operations.

10 . The method of claim 1 , wherein the plurality of MRAM layers includes a first magnetic layer, a second magnetic layer, the tunnel barrier layer between the first magnetic layer and the second magnetic layer, and an underlayer disposed below the second magnetic layer, wherein the underlayer includes a dielectric material, and wherein the tunnel barrier layer includes a non-magnetic insulating material.

11 . The method of claim 10 , wherein etching through the plurality of MRAM layers includes ion beam etching through the first magnetic layer, the tunnel barrier layer, and the second magnetic layer without etching through the underlayer.

12 . The method of claim 10 , wherein etching through the plurality of MRAM layers includes reactive ion etching (ME) through the first magnetic layer and ion beam etching through the tunnel barrier layer.

13 . The method of claim 10 , wherein etching through the plurality of MRAM layers includes etching through the first magnetic layer, the tunnel barrier layer, and the second magnetic layer, wherein etching through the plurality of MRAM layers is stopped on the underlayer.

14 . The method of claim 1 , wherein ion beam etching through at least the tunnel barrier layer includes applying a first ion beam to the substrate having an energy between about 200 eV and about 10,000 eV, and wherein performing an IBE trim etch includes applying a second ion beam to the substrate having an energy between about 20 eV and about 400 eV.

15 . The method of claim 1 , wherein performing an IBE trim etch occurs without etching through an underlayer disposed below the plurality of MRAM layers.

16 . The method of claim 1 , wherein the electrically conductive materials include tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), cobalt (Co), nickel (Ni), iron (Fe) platinum (Pt), ruthenium (Ru), or combinations thereof, and wherein the sidewalls of the patterned MRAM stacks are substantially free of the electrically conductive materials deposited on the sidewalls of the patterned MRAM stacks after performing the IBE trim etch.

17 . The method of claim 1 , further comprising:
conformally depositing an encapsulation material on at least the sidewalls of the patterned MRAM stacks after performing the IBE trim etch.

18 . An apparatus for performing ion beam etching, the apparatus comprising:
an ion beam source chamber; a processing chamber coupled to the ion beam source chamber; a controller configured to provide instructions to perform the following operations:
dispose a plurality of MRAM layers on a substrate in the processing chamber, the plurality of MRAM layers including one or more magnetic layers and a tunnel barrier layer;
etch through the plurality of MRAM layers disposed on the substrate to form patterned MRAM stacks, wherein the etch through the plurality of MRAM layers includes ion beam etching (IBE) through at least the tunnel barrier layer;
form a gapfill dielectric material in spaces between the patterned MRAM stacks; and
perform an IBE trim etch to remove at least some of the gapfill dielectric material and electrically conductive materials deposited on sidewalls of the patterned MRAM stacks.

19 . The apparatus of claim 18 , wherein the controller configured to provide instructions to form the gapfill dielectric material is further configured to provide instructions to perform the following operation:
deposit the gapfill dielectric material in the spaces between the patterned MRAM stacks and over the patterned MRAM stacks.

20 . The apparatus of claim 19 , wherein the controller configured to provide instructions to form the gapfill dielectric material is further configured to provide instructions to perform the following operation:
selectively etch the gapfill dielectric material to an etch depth above the depth of the tunnel barrier layer.

21 . The apparatus of claim 20 , wherein the controller is further configured to provide instructions to perform the following operation:
planarize the gapfill dielectric material deposited over the patterned MRAM stacks before selectively etching the gapfill dielectric material.

22 . The apparatus of claim 18 , wherein the gapfill dielectric material includes one or both of silicon nitride and silicon oxide.

23 . The apparatus of claim 18 , wherein the controller configured to provide instructions to ion beam etch through at least the tunnel barrier layer is further configured to provide instructions to apply a first ion beam to the substrate having an energy between about 200 eV and about 10,000 eV, and wherein the controller configured to provide instructions to perform the IBE trim etch is further configured to apply a second ion beam to the substrate having an energy between about 20 eV and about 400 eV.

24 . The apparatus of claim 18 , wherein the gapfill dielectric material is formed to a sufficient depth above an underlayer disposed between the substrate and the plurality of MRAM layers so that performing the IBE trim etch does not cause recess into the underlayer.

Assignees

• Lam Res Corp

Inventors

• Lill Thorsten
• Berry Iii Ivan L

Classifications

• H10N50/85

  Materials of the active region · CPC title

• G11C11/161

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• H01L43/02

  Electricity · mapped topic

• H01L27/222

  Electricity · mapped topic

• H01L43/10

  Electricity · mapped topic