Semiconductor memory device
US-2019259775-A1 · Aug 22, 2019 · US
Memory device
US2022123113A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2022123113-A1 |
| Application number | US-202117231515-A |
| Country | US |
| Kind code | A1 |
| Filing date | Apr 15, 2021 |
| Priority date | Oct 16, 2020 |
| Publication date | Apr 21, 2022 |
| Grant date | — |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
The present technology includes a memory device. The memory device includes a stack structure including word lines and a select line, a vertical hole vertically penetrating the stack structure, and a memory layer, a channel layer, and a plug, sequentially formed along an inner side surface of the vertical hole. The plug includes a material layer having a fixed negative charge.
First claim
Opening claim text (preview).
What is claimed is: 1 . A memory device comprising: a stack structure including word lines and a select line; a vertical hole vertically penetrating the stack structure; and a memory layer, a channel layer, and a plug, sequentially formed along an inner side surface of the vertical hole, wherein the plug includes a material layer having a fixed negative charge. 2 . The memory device of claim 1 , wherein the material layer includes an Al 2 O 3 layer. 3 . The memory device of claim 1 , wherein the plug includes: a first insulating layer; the material layer formed on the first insulating layer; and a capping pattern formed on the material layer. 4 . The memory device of claim 3 , wherein the first insulating layer includes an oxide layer, and the capping pattern includes doped silicon. 5 . The memory device of claim 3 , wherein the material layer is formed at a position adjacent to the select line in the plug. 6 . The memory device of claim 5 , wherein a bottom surface of the material layer is located between a bottom surface and a top surface of the select line. 7 . The memory device of claim 5 , wherein a top surface of the material layer is located in a region higher than a top surface of the select line. 8 . The memory device of claim 1 , wherein the plug includes a first insulating layer, the material layer, and a second insulating layer, and wherein the material layer is disposed between the first and second insulating layers. 9 . The memory device of claim 8 , wherein a bottom surface of the material layer is located between a bottom surface and a top surface of the select line. 10 . The memory device of claim 8 , wherein a top surface of the material layer is located at a height greater than a height at which a top surface of the select line is located. 11 . The memory device of claim 1 , wherein the plug Includes a first insulating layer and the material layer, and wherein a position of a top surface of the material layer is equal to that of a top surface of the plug. 12 . A memory device comprising: a stack structure including word lines and a plurality of select lines; a vertical hole vertically penetrating the stack structure; and a memory layer, channel layer, and a plug, sequentially formed along an inner side surface of the vertical hole, wherein the plug includes a material layer having a fixed negative charge. 13 . The memory device of claim 12 , wherein the material layer includes an Al 2 O 3 layer. 14 . The memory device of claim 12 , wherein the plug includes: a first insulating layer; the material layer formed on the first insulating layer; and a capping pattern formed on the material layer. 15 . The memory device of claim 14 , wherein a bottom surface of the material layer is located between a bottom surface of a select line located at a lowermost end among the plurality of select lines and a top surface of a select line located at an uppermost end among the plurality of select lines. 16 . The memory device of claim 14 , wherein the capping pattern includes doped silicon. 17 . The memory device of claim 12 , wherein the plug includes a first insulating layer, the material layer, and a second insulating layer, and wherein the material layer is disposed between the first and second insulating layers. 18 . The memory device of claim 17 , wherein a bottom surface of the material layer is located between a bottom surface of a select line located at a lowermost end among the plurality of select lines and a top surface of a select line located at an uppermost end among the plurality of select lines. 19 . The memory device of claim 17 , wherein a top surface of the material layer is located on the top of a top surface of a select line located at an uppermost end among the plurality of select lines. 20 . The memory device of claim 12 , wherein the plug includes a first insulating layer and the material layer, and wherein a position of a top surface of the material layer is equal to that of a top surface of the plug.
Assignees
Inventors
Classifications
IGFETs having charge trapping gate insulators, e.g. MNOS transistors · CPC title
- H10D64/118Primary
Electrodes comprising insulating layers having particular dielectric or electrostatic properties, e.g. having static charges · CPC title
- H10D64/037Primary
comprising charge-trapping insulators · CPC title
- H01L29/408Primary
Electricity · mapped topic
Electricity · mapped topic
Patent family
Related publications grouped by family.
External sources
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US2022123113A1 cover?
- The present technology includes a memory device. The memory device includes a stack structure including word lines and a select line, a vertical hole vertically penetrating the stack structure, and a memory layer, a channel layer, and a plug, sequentially formed along an inner side surface of the vertical hole. The plug includes a material layer having a fixed negative charge.
- Who is the assignee on this patent?
- Sk Hynix Inc
- What technology area does this patent fall under?
- Primary CPC classification H10D64/118. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu Apr 21 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).