Semiconductor memory device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9929171-B2
Application number	US-201615241599-A
Country	US
Kind code	B2
Filing date	Aug 19, 2016
Priority date	Mar 8, 2016
Publication date	Mar 27, 2018
Grant date	Mar 27, 2018

Abstract

A semiconductor memory device according to an embodiment comprises: a semiconductor substrate; a semiconductor layer provided extending in a first direction above the semiconductor substrate, on the semiconductor substrate; a first insulating layer provided on a side surface of the semiconductor layer; a charge accumulation layer provided on a side surface of the first insulating layer; a block insulating layer provided on a side surface of the charge accumulation layer; and a plurality of conductive layers stacked in the first direction via an insulating layer, in a periphery of the block insulating layer. The block insulating layer includes: a first block insulating layer; and a second block insulating layer that has a permittivity which is higher than that of the first block insulating layer. A lower end of the second block insulating layer is positioned more upwardly than a lower end of the first insulating layer.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a semiconductor substrate;
a semiconductor layer provided above the semiconductor substrate and extending in a first direction intersecting a main surface of the semiconductor substrate;
a first insulating layer provided on a side surface of the semiconductor layer;
a charge accumulation layer provided on a side surface of the first insulating layer;
a block insulating layer provided on a side surface of the charge accumulation layer; and
a plurality of conductive layers stacked in the first direction via a plurality of insulating layers, in a periphery of the block insulating layer, wherein
the block insulating layer continuously extends in the first direction along the plurality of conductive layers,
the block insulating layer including:
a first block insulating layer and a second block insulating layer that has a permittivity which is higher than that of the first block insulating layer, and
a lower end of the second block insulating layer being positioned more upwardly than a lower end of the first insulating layer.

2. The semiconductor memory device according to claim 1 , wherein
the semiconductor layer is configured from:
a first semiconductor layer extending in the first direction; and
a second semiconductor layer covering a side surface of the first semiconductor layer,
a lower end of the second semiconductor layer being positioned more upwardly than a lower end of the first semiconductor layer.

3. The semiconductor memory device according to claim 2 , wherein
an interface of the first semiconductor layer and the second semiconductor layer includes oxygen atoms.

4. The semiconductor memory device according to claim 1 , wherein
a lower end of the charge accumulation layer is positioned more downwardly than a lower end of the block insulating layer and more downwardly than the lower end of the first insulating layer.

5. The semiconductor memory device according to claim 4 , wherein
the charge accumulation layer is configured from:
a first portion extending in the first direction to cover the side surface of the first insulating layer, the first insulating layer being a tunnel insulating layer; and
a second portion projecting in a direction directed from a lower end of the first portion to the semiconductor layer, an end of the second portion contacting the semiconductor layer.

6. The semiconductor memory device according to claim 1 , wherein
a lower end of the charge accumulation layer is positioned more upwardly than a lower end of the block insulating layer.

7. The semiconductor memory device according to claim 6 , wherein
the block insulating layer is configured from:
a first portion extending in the first direction to cover the side surface of the charge accumulation layer; and
a second portion projecting in a direction directed from a lower end of the first portion to the semiconductor layer, an end of the second portion contacting the first insulating layer, the first insulating layer being a tunnel insulating layer.

8. The semiconductor memory device according to claim 1 , further comprising an epitaxial layer provided on the semiconductor substrate, wherein
the semiconductor layer, the first insulating layer, the charge accumulation layer, and the block insulating layer are provided on the epitaxial layer,
the first insulating layer being a tunnel insulating layer.

9. The semiconductor memory device according to claim 8 , wherein
an upper surface of the epitaxial layer is positioned between an upper surface of a first layer of the plurality of conductive layers which is the first closest to the semiconductor substrate and a lower surface of a second layer of the plurality of conductive layers which is the second closest to the semiconductor substrate.

10. The semiconductor memory device according to claim 9 , wherein
a second insulating layer is provided between the first layer of the plurality of conductive layers and the epitaxial layer.

11. The semiconductor memory device according to claim 8 , wherein
a surface of the epitaxial layer has a stepped shape whose height becomes lower from an outer side to an inner side.

12. The semiconductor memory device according to claim 1 , wherein
the plurality of insulating layers are stacked above the semiconductor substrate in the first direction with the plurality of conductive layers interposed therebetween, the plurality of insulating layers including a third insulating layer which is the second closest to the semiconductor substrate,
an average thickness of the third insulating layer is greater than an average thickness of another insulating layer of the plurality of insulating layers stacked in the first direction.

13. The semiconductor memory device according to claim 1 , wherein
the first block insulating layer is a silicon oxide layer.

14. The semiconductor memory device according to claim 1 , wherein
the second block insulating layer includes Hf, Al, Zr, Ti, or Ta.

15. The semiconductor memory device according to claim 2 , wherein no block insulating layer directly contacts the first and second semiconductor layers.

Assignees

• Toshiba Memory Corp

Inventors

• Aoyama Kenji

Classifications

• H01L27/11556

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L27/11568

  Electricity · mapped topic

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title