Scalable-pixel-size image sensor

Patent metadata

Field	Value
Publication number	US-2022102403-A1
Application number	US-202117401170-A
Country	US
Kind code	A1
Filing date	Aug 12, 2021
Priority date	Nov 20, 2019
Publication date	Mar 31, 2022
Grant date	—

Abstract

Photodetection elements within an integrated-circuit pixel array are dynamically configurable to any of at least three uniform-aspect-ratio, size-scaled pixel footprints through read-out-time control of in-pixel transfer gates associated with respective photodetection elements and binning transistors coupled between the transfer gates for respective clusters of the photodetection elements and a shared reset node.

First claim

1 - 26 . (canceled)

27 . An image sensor comprising:
first and second subpixels centered on a first axis and each having a respective floating diffusion node coupled to a plurality of photodetection elements via corresponding transfer gates; third and fourth subpixels centered on a second axis parallel to the first axis and each having a respective floating diffusion node coupled to a plurality of photodetection elements via corresponding transfer gates; a reset transistor coupled between a reset voltage supply and a shared reset node; and first, second, third and fourth binning transistors connected directly between the floating diffusion nodes of the first, second, third and fourth subpixels, respectively, and the shared reset node.

28 . The image sensor of claim 27 further comprising first, second, third and fourth readout circuits coupled to the floating diffusion nodes of the first, second, third and fourth sub-pixels, respectively, wherein each of the first, second, third and fourth readout circuits includes (i) a respective readout transistor having a gate terminal coupled to a respective one of the floating diffusion nodes of the first, second, third and fourth sub-pixels, and (ii) a respective read-select transistor coupled to a source terminal of the respective readout transistor.

29 . The image sensor of claim 28 wherein the respective read-select transistor within each of the first, second, third and fourth readout circuits is coupled drain-to-source between the source terminal of the respective readout transistor and a respective column output line.

30 . The image sensor of claim 29 further comprising read-out control circuitry to switch on the read-select transistors within each of the first, second, third and fourth readout circuits concurrently to concurrently drive readout signals onto the respective column output lines to which the read-select transistors are coupled.

31 . The integrated-circuit pixel of claim 28 wherein the respective read-select transistor within each of the first, second, third and fourth readout circuits is coupled drain-to-source between the source terminal of the respective readout transistor and a shared column output line.

32 . The integrated-circuit pixel of claim 28 wherein a drain terminal of each respective readout transistor is coupled to a readout supply voltage and a source terminal of each respective read-select transistor is biased by a current source.

33 . The image sensor of claim 27 further comprising a capacitive element and a gain-control transistor coupled between the capacitive element and the shared reset node.

34 . The image sensor of claim 33 wherein the gain-control transistor is coupled between the shared reset node and the reset transistor such that both the reset transistor and the gain-control transistor must be rendered to a drain-to-source conducting state to charge the shared reset node via the reset voltage supply.

35 . The image sensor of claim 27 wherein each individual photodetection element of the plurality of photodetection elements within each of the first, second, third and fourth sub-pixels has a first aspect ratio, and wherein each of the first, second, third and fourth subpixels also has the first aspect ratio.

36 . The image sensor of claim 35 wherein the first, second, third and fourth subpixels collectively have the first aspect ratio.

37 . The image sensor of claim 27 wherein the first, second, third and fourth subpixels are disposed in respective quadrants of a pixel unit.

38 . The image sensor of claim 27 wherein the first and third subpixels are centered on a third axis perpendicular to the first and second axes, and the second and fourth subpixels are centered on a fourth axis parallel to the third axis.

39 . The image sensor of claim 27 wherein the shared reset node has a capacitance that nominally matches a capacitance of each individual one of the respective floating diffusion nodes of the first, second, third and fourth sub-pixels.

40 . The image sensor of claim 39 further comprising a capacitive element and a gain-control transistor coupled between the capacitive element and the shared reset node, the capacitive element having a capacitance that nominally matches the capacitance of the shared reset node multiplied by an integer greater than one.

41 . The image sensor of claim 27 further comprising micro-lenses disposed respectively over individual photodetection elements that constitute each of the plurality of photodetection elements within the first, second, third and fourth subpixels.

42 . The image sensor of claim 27 further comprising a color filter array having first, second, third and fourth color filter elements disposed respectively over the first, second, third and fourth subpixels.

43 . The image sensor of claim 42 wherein the first, second, third and fourth color filter elements comprise two green color filter elements, a red color filter element and a blue color filter element disposed in a Bayer pattern.

44 . An integrated-circuit pixel comprising:
a plurality of photodetection elements; and readout circuitry to generate:
a first readout signal corresponding to photocharge accumulated within a single one of the photodetection elements in response to control signals that specify a first effective pixel size, the single one of the photodetection elements having a first aspect ratio;
a second readout signal corresponding to photocharge accumulated collectively within a single cluster of the photodetection elements in response to control signals that specify a second effective pixel size, the single cluster of the photodetection elements spanning a first area having the first aspect ratio and including more than one and fewer than all of the photodetection elements; and
a third readout signal corresponding to photocharge accumulated collectively within multiple clusters of the photodetection elements in response to control signals that specify a third effective pixel size, the multiple clusters of the photodetection elements collectively spanning a second area larger than the first area and having the first aspect ratio, and each individual cluster of the multiple clusters including more than one of the photodetection elements.

45 . The integrated-circuit pixel of claim 44 wherein the readout circuitry to generate the first, second and third readout signals comprises (i) transfer gates coupled respectively to the photodetection elements within each of the multiple clusters of the photodetection elements, (ii) a plurality of floating diffusion nodes corresponding respectively to the multiple clusters of the photodetection elements and coupled respectively thereto via the transfer gates, and (iii) a plurality of transistor readout circuits coupled respectively to the plurality of floating diffusion nodes.

46 . The integrated-circuit pixel of claim 45 further comprising:
a shared reset node coupled to the plurality of floating diffusion nodes via respective binning transistors such that the quantity of binning transistors matches the quantity of clusters of the photodetection elements; and
a reset transistor coupled between the shared reset node and a reset voltage supply line.

47 . An integrated-circuit pixel comprising:
a plurality of photodetection elements; and means for generating:
a first readout signal corresponding to photocharge accumulated within a single one of the photodetection elements in response to control signals t

Assignees

• Gigajot Tech Inc

Inventors

• Ma Jiaju
• Guidash Michael

Classifications

• H04N25/778

  comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself · CPC title

• H04N25/59

  by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance · CPC title

• H04N25/65

  applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS · CPC title

• H04N25/78

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title

• H10F39/153

  Two-dimensional or three-dimensional array CCD image sensors · CPC title