Semiconductor device and method for fabricating the same

US2022102193A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2022102193-A1
Application numberUS-202117152390-A
CountryUS
Kind codeA1
Filing dateJan 19, 2021
Priority dateSep 25, 2020
Publication dateMar 31, 2022
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor device including: a trench defining an active region in a substrate; a first semiconductor liner formed over the trench; a second semiconductor liner formed over the first semiconductor liner; and a device isolation layer formed over the second semiconductor liner and filling the trench. Disclosed is also a method for fabricating a semiconductor device, the method including: forming a trench defining an active region in a substrate; forming a plurality of semiconductor liners over the trench; performing pretreatment before forming each of the semiconductor liners; and performing post-treatment after forming each of the semiconductor liners.

First claim

Opening claim text (preview).

What is claimed is: 1 . A method for fabricating a semiconductor device, the method comprising: forming a trench defining an active region in a substrate; forming a plurality of semiconductor liners over the trench; performing pretreatment before forming each of the semiconductor liners; and performing post-treatment after forming each of the semiconductor liners. 2 . The method of claim 1 , wherein the performing of the pretreatment comprises: replacing a contaminant, generated before forming each of the semiconductor liners, with a sacrificial material; and performing heat treatment to remove the sacrificial material. 3 . The method of claim 2 , wherein the replacing of the contaminant with the sacrificial material is performed using a reactive gas having reactivity with the contaminant. 4 . The method of claim 3 , wherein the reactive gas is formed using ammonia (NH 3 ) gas, nitrogen trifluoride (NF 3 ) gas and hydrogen (H 2 ) gas. 5 . The method of claim 2 , wherein the contaminant comprises silicon oxide, and the sacrificial material comprises ammonium hexafluorosilicate ((NH 4 ) 2 SiF 6 ). 6 . The method of claim 1 , wherein the post-treatment is performed at a higher temperature than the pretreatment. 7 . The method of claim 1 , wherein the post-treatment is performed through an annealing process or a rapid thermal process (RTP). 8 . The method of claim 1 , wherein the post-treatment is performed under a gas atmosphere containing one of nitrogen (N 2 ) and hydrogen (H 2 ). 9 . The method of claim 1 , further comprising cleaning each of the semiconductor liners, before the performing of the post-treatment. 10 . The method of claim 1 , wherein the plurality of semiconductor liners are formed by stacking polysilicon (poly-Si). 11 . The method of claim 1 , wherein the pretreatment and the forming of the semiconductor liners are performed in situ. 12 . The method of claim 1 , wherein the post-treatment is performed in one of a single equipment and a furnace equipment. 13 . A method for fabricating a semiconductor device, the method comprising: forming a trench defining an active region in a substrate; replacing a native oxide formed on the trench with a solid salt; sublimating the solid salt to expose a surface of the trench; forming a first polysilicon liner over the trench; performing post-treatment to remove a contaminant formed on the first polysilicon liner; replacing a native oxide formed on the first polysilicon liner with a solid salt; sublimating the solid salt to expose a surface of the first polysilicon liner; forming a second polysilicon liner over the first polysilicon liner; and forming a device isolation layer filling the trench over the second polysilicon liner. 14 . The method of claim 13 , wherein the replacing of the native oxide with the solid salt is performed using a reactive gas having reactivity with the native oxide. 15 . The method of claim 14 , wherein the reactive gas is formed using ammonia (NH 3 ) gas, nitrogen trifluoride (NF 3 ) gas and hydrogen (H 2 ) gas. 16 . The method of claim 13 , wherein the solid salt comprises ammonium hexafluorosilicate ((NH 4 ) 2 SiF 6 ). 17 . The method of claim 13 , wherein the post-treatment is performed at a higher temperature than the sublimating of the solid salt. 18 . The method of claim 13 , wherein the post-treatment is performed through an annealing process or a rapid thermal process (RTP). 19 . The method of claim 13 , wherein the post-treatment is performed under a gas atmosphere containing one of nitrogen (N 2 ) and hydrogen (H 2 ). 20 . The method of claim 13 , further comprising cleaning the first polysilicon liner, before the performing of the post-treatment. 21 . The method of claim 13 , wherein the post-treatment is performed in one of a single equipment and a furnace equipment.

Assignees

Inventors

Classifications

  • In-situ cleaning · CPC title

  • consisting of two layers · CPC title

  • Silicon, silicon germanium or germanium · CPC title

  • characterised by treatments done after the formation of the materials · CPC title

  • comprising concurrently refilling multiple trenches having different shapes or dimensions · CPC title

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Frequently asked questions

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What does patent US2022102193A1 cover?
A semiconductor device including: a trench defining an active region in a substrate; a first semiconductor liner formed over the trench; a second semiconductor liner formed over the first semiconductor liner; and a device isolation layer formed over the second semiconductor liner and filling the trench. Disclosed is also a method for fabricating a semiconductor device, the method including: for…
Who is the assignee on this patent?
Sk Hynix Inc
What technology area does this patent fall under?
Primary CPC classification H10W10/014. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Mar 31 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 7 related publications on this page (citations in our corpus or others sharing the same primary CPC).