Memory device and electronic system including the same

Patent metadata

Field	Value
Publication number	US-2022085037-A1
Application number	US-202117212029-A
Country	US
Kind code	A1
Filing date	Mar 25, 2021
Priority date	Sep 16, 2020
Publication date	Mar 17, 2022
Grant date	—

Abstract

A memory device and an electronic system, the memory device including a substrate; a ground selection line on the substrate, a cutting portion cutting the ground selection line; a first insulation layer and a first word line stacked immediately above the ground selection line; and second insulation layers and second word lines alternately stacked on the first word line, wherein the first word line includes a first portion laterally offset from the cutting portion and a second portion overlying the cutting portion, the first portion of the first word line has a first thickness, and the second portion of the first word line has a second thickness less than the first thickness.

First claim

What is claimed is:

1 . A memory device, comprising:
a substrate; a ground selection line on the substrate, a cutting portion cutting the ground selection line; a first insulation layer and a first word line stacked immediately above the ground selection line; and second insulation layers and second word lines alternately stacked on the first word line, wherein: the first word line includes a first portion laterally offset from the cutting portion and a second portion overlying the cutting portion, the first portion of the first word line has a first thickness, and the second portion of the first word line has a second thickness less than the first thickness.

2 . The memory device as claimed in claim 1 , wherein:
the cutting portion includes a first opening passing through the first insulation layer and cutting the ground selection line, and a lower insulation pattern is in the first opening.

3 . The memory device as claimed in claim 2 , wherein an upper surface of the lower insulation pattern protrudes above a lower surface of the first word line at the first portion of the first word line.

4 . The memory device as claimed in claim 2 , wherein the lower insulation pattern includes silicon oxide.

5 . The memory device as claimed in claim 1 , wherein:
an upper surface of the first word line is flat at the first portion and the second portion, and a lower surface of the first portion of the first word line is inwardly recessed relative to a lower surface of the second portion of the first word line such that a lower surface of the first word line is not flat.

6 . The memory device as claimed in claim 1 , wherein each of the second word lines has the first thickness.

7 . The memory device as claimed in claim 1 , wherein upper surfaces of the second word lines are flat and lower surfaces of the second word lines are flat.

8 . The memory device as claimed in claim 1 , wherein the first insulation layer has a thickness greater than a thickness of the second insulation layer.

9 . The memory device as claimed in claim 1 , further comprising:
a circuit pattern on the substrate; and a base semiconductor pattern on the circuit pattern, wherein the ground selection line is on the base semiconductor pattern.

10 . A memory device, comprising:
a substrate; a circuit pattern on the substrate; a base semiconductor pattern on the circuit pattern; a ground selection line on the base semiconductor pattern, a cutting portion cutting the ground selection line; a first insulation layer and a first word line stacked immediately above the ground selection line; a lower insulation pattern passing through a portion of the first insulation layer and the cutting portion; second insulation layers and second word lines alternately stacked on the first word line; and a channel structure passing through the ground selection line, the first insulation layer, the first word line, the second insulation layers, and the second word lines, the channel structure extending in a vertical direction, wherein: the first word line includes a first portion laterally offset from the cutting portion and a second portion overlying the cutting portion, the first portion of the first word line has a first thickness, the second portion of the first word line has a second thickness less than the first thickness, and an upper surface of the lower insulation pattern protrudes above a lower surface of the first word line at the first portion of the first word line.

11 . The memory device as claimed in claim 10 , wherein:
an upper surface of the first word line is flat at the first portion and the second portion, and a lower surface of the first portion of the first word line is inwardly recessed relative to a lower surface of the second portion of the first word line such that a lower surface of the first word line is not flat.

12 . The memory device as claimed in claim 10 , wherein the first thickness is less than the second thickness.

13 . The memory device as claimed in claim 12 , wherein each of the second word lines has the first thickness.

14 . The memory device as claimed in claim 10 , wherein upper and lower surfaces of the second word lines are flat.

15 . The memory device as claimed in claim 10 , further comprising a gate pattern of an erase control transistor below the ground selection line on the base semiconductor pattern.

16 . The memory device as claimed in claim 10 , wherein the lower insulation pattern includes silicon oxide.

17 . The memory device as claimed in claim 10 , wherein:
the ground selection line, the first insulation layer, the first word line, the second insulation layers, and the second word lines stacked in the vertical direction constitute a cell stacked structure, and each of a plurality of the cell stacked structures extend in a first direction.

18 . The memory device as claimed in claim 17 , further comprising trenches extending in the first direction between the cell stacked structures and a connection portion between the trenches, wherein the cutting portion is under the connection portion.

19 . An electronic system, comprising:
a memory device; and a controller configured to control the memory device, the controller being electrically connected to the memory device through an input/output pad of the memory device, wherein the memory device includes:
a substrate;
a peripheral circuit pattern on the substrate;
a ground selection line on the substrate, a cutting portion cutting the ground selection line;
a first insulation layer and a first word line stacked immediately above the ground selection line;
second insulation layers and second word lines alternately stacked on the first word line; and
the input/output pad, the input/output pad being electrically connected to the peripheral circuit pattern,
wherein the first word line includes a first portion laterally offset from the cutting portion and a second portion overlying the cutting portion, wherein the first portion of the first word line has a first thickness, and wherein the second portion of the first word line has a second thickness less than the first thickness.

20 . The electronic system as claimed in claim 19 , wherein:
the cutting portion includes a first opening passing through the first insulation layer and cutting the ground selection line, and a lower insulation pattern fills the first opening, the lower insulation pattern having an upper surface protruding above a lower surface of the first word line at the first portion of the first word line.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Chung Giyong
• Kim Jaehyung

Classifications

• H01L27/11556

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic

• H01L27/1157 Primary

  Electricity · mapped topic

• H01L27/11524

  Electricity · mapped topic

• H01L27/11573

  Electricity · mapped topic