Nonvolatile memory device and method of detecting defective memory cell block of nonvolatile memory device

Patent metadata

Field	Value
Publication number	US-2022051738-A1
Application number	US-202117397012-A
Country	US
Kind code	A1
Filing date	Aug 9, 2021
Priority date	Aug 12, 2020
Publication date	Feb 17, 2022
Grant date	—

Abstract

A method of detecting, by a nonvolatile memory system, a defective memory cell block from among memory cell blocks, includes performing, after performing an erase operation, a read operation on at least some memory cells included in a target memory cell block based on an off-cell detection voltage that is different from a read reference voltage that distinguishes an off-cell on which no data is written from an on-cell on which data is written; counting a number of hard off-cells having a higher threshold voltage than the off-cell detection voltage from among the memory cells based on a result of performing the read operation; and identifying whether the target memory cell block is a defective memory cell block based on the number of counted hard off-cells.

First claim

1 . A method of detecting a defective memory cell block in a nonvolatile memory system, the method comprising:
performing, after an erase operation, a read operation on one or more memory cells included in a target memory cell block based on an off-cell detection voltage that is different from a read reference voltage; counting a number of hard off-cells having a higher threshold voltage than the off-cell detection voltage among the one or more memory cells based on a result of performing the read operation; and identifying whether the target memory cell block is a defective memory cell block based on the number of hard off-cells.

2 . The method of claim 1 , wherein the performing of the read operation comprises setting, as the off-cell detection voltage, a value between a threshold voltage level of an erased memory cell and a threshold voltage level of a hard off-cell.

3 . The method of claim 1 , wherein the performing of the read operation comprises:
applying the off-cell detection voltage to each of a plurality of word lines connected to the target memory cell block; and measuring an output current from a cell string connected to the target memory cell.

4 . The method of claim 3 , wherein the counting the number of hard off-cells comprises identifying whether the target memory cell is a hard off-cell based on the output current.

5 . The method of claim 4 , wherein the counting the number of hard off-cells comprises identifying the target memory cell as the hard off-cell based on the output current being less than a threshold current.

6 . The method of claim 1 , wherein the identifying whether the memory cell block is the defective memory cell block comprises:
comparing the number of hard off-cells with a reference number of off-cells; and identifying whether the target memory cell block is the defective memory cell block based on a result of the comparing.

7 . The method of claim 6 , wherein the reference number of off-cells comprises an initial number of off-cells corresponding to string select lines of the target memory cell block.

8 . The method of claim 6 , wherein the identifying whether the memory cell block is the defective memory cell block comprises identifying the memory cell block as the defective memory cell block based on the number of hard off-cells exceeding the reference number of off-cells.

9 . A nonvolatile memory system comprising:
a memory device including a plurality of memory cell blocks; and a memory controller comprising: a command generator configured to output an off-cell detection command signal to direct the memory device to perform a hard off-cell detection operation after the memory device performs an erase operation; and a defective memory cell block identifier configured to output a signal indicating whether a target memory cell block is a defective memory cell block based on a number of hard off-cells among one or more memory cells included in the target memory cell block according to the off-cell detection command signal, wherein the memory device is configured to perform, based on the off-cell detection command signal, a read operation on the one or more memory cells based on an off-cell detection voltage that is different from a read reference voltage.

10 . The nonvolatile memory system of claim 9 , wherein the memory device comprises a voltage generator configured to output, as the off-cell detection voltage, a value between a threshold voltage level of an erased memory cell and a threshold voltage level of a hard off-cell, based on the off-cell detection command signal.

11 . The nonvolatile memory system of claim 9 , wherein the memory device comprises:
a memory cell array in which a plurality of word lines are connected to memory cells of target cell string such that a voltage is applied to the memory cells; a row decoder configured to apply the off-cell detection voltage to a target memory cell via a target word line from among the plurality of word lines; and a sensing amplifier configured to receive an output current from the target cell string based on the off-cell detection voltage.

12 . The nonvolatile memory system of claim 11 , wherein the sensing amplifier outputs a signal indicating whether the target memory cell is a hard off-cell, based on the output current.

13 . The nonvolatile memory system of claim 12 , wherein the sensing amplifier outputs a signal indicating that the target memory cell is the hard off-cell based on the output current being less than a threshold current.

14 . The nonvolatile memory system of claim 9 , wherein the memory device comprises a pager buffer configured to count the number of hard off-cells from among the one or more memory cells based on a result of the performing of the read operation.

15 . The nonvolatile memory system of claim 9 , wherein the memory controller comprises an off-cell counter configured to receive a result of the performing of the read operation and count the number of hard off-cells of the one or more memory cells based on a result of the performing of the read operation.

16 . The nonvolatile memory system of claim 9 , wherein the memory device comprises an off-cell information storage block configured to store a block address, a string select line (SSL) address, and information of a reference number of off-cells corresponding to the block address and the SSL address,
wherein the defective memory cell block identifier configured to identify whether the memory cell block is the defective memory cell block by comparing the reference number of off-cells with the number of hard off-cells.

17 . The nonvolatile memory system of claim 16 , wherein, in the off-cell information storage block, an initial number of off-cells corresponding to each string select line of the memory cell blocks is stored to correspond to the block address and the SSL address.

18 . The nonvolatile memory system of claim 16 , wherein the defective memory cell block identifier is further configured to identify the target memory cell block as the defective memory cell block based on the number of hard off-cells exceeding the reference number of off-cells.

19 . A nonvolatile memory controller comprising:
a memory storing one or more instructions; and a processor configured to execute the one or more instructions to implement: a command generator configured to output an off-cell detection command signal to direct a memory device to perform a hard off-cell detection operation after the memory device performs an erase operation; and a defective memory cell block identifier configured to output a signal indicating whether a memory cell block including a target cell string is a defective memory cell block based on a number of hard off-cells among one or more memory cells included in a target memory cell block according to the off-cell detection command signal.

20 . The nonvolatile memory controller of claim 19 , wherein the command generator is further configured to output a command signal directing to set, as the off-cell detection voltage, a value between a threshold voltage level of an erased memory cell and a threshold voltage level of a hard off-cell.

21 - 25 . (canceled)

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Myungnam
• Kim Daehan
• Jung Wontaeck

Classifications

• G11C16/3445 Primary

  Circuits or methods to verify correct erasure of nonvolatile memory cells · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• G11C29/76

  using address translation or modifications · CPC title