Sense amplifier, memory, and method for controlling sense amplifier

Patent metadata

Field	Value
Publication number	US-2022051713-A1
Application number	US-202117474172-A
Country	US
Kind code	A1
Filing date	Sep 14, 2021
Priority date	Aug 13, 2020
Publication date	Feb 17, 2022
Grant date	—

Abstract

A sense amplifier includes an amplification module and a control module electrically connected to the amplification module. Herein, in a case of reading a data in a memory cell on a first bit line, at an offset compensation stage of the sense amplifier, the control module is arranged to configure the amplification module to include a first diode structure, a first current mirror structure, and a first inverter with an input terminal and an output terminal connected to each other. In a case of reading a data in a memory cell on a second bit line, at the offset compensation stage of the sense amplifier, the control module is arranged to configure the amplification module to include a second diode structure, a second current mirror structure, and a second inverter with an input terminal and an output terminal connected to each other.

First claim

1 . A sense amplifier, comprising:
an amplification circuit arranged to read a data in a memory cell on a first bit line or a second bit line; and a control circuit, electrically connected to the amplification circuit; wherein in a case of reading the data in the memory cell on the first bit line, at an offset compensation stage of the sense amplifier, the control circuit is arranged to configure the amplification circuit to comprise a first diode structure, a first current mirror structure, and a first inverter with an input terminal and an output terminal connected to each other; in a case of reading the data in the memory cell on the second bit line, at the offset compensation stage of the sense amplifier, the control circuit is arranged to configure the amplification circuit to comprise a second diode structure, a second current mirror structure, and a second inverter with an input terminal and an output terminal connected to each other.

2 . The sense amplifier of claim 1 , wherein the amplification circuit comprises:
a first P-channel Metal Oxide Semiconductor (PMOS) transistor; a second PMOS transistor; a first N-channel Metal Oxide Semiconductor (NMOS) transistor, a gate of the first NMOS transistor being connected to the first bit line, and a drain of the first NMOS transistor being connected to a drain of the first PMOS transistor through a first node; and a second NMOS transistor, a gate of the second NMOS transistor being connected to the second bit line, and a drain of the second NMOS transistor being connected to a drain of the second PMOS transistor through a second node; wherein in the case of reading the data in the memory cell on the first bit line, at the offset compensation stage of the sense amplifier, the second NMOS transistor is configured as the first diode structure, the first PMOS transistor and the second PMOS transistor are configured as the first current mirror structure, and the first PMOS transistor and the first NMOS transistor are configured as the first inverter with the input terminal and the output terminal connected to each other; in the case of reading the data in the memory cell on the second bit line, at the offset compensation stage of the sense amplifier, the first NMOS transistor is configured as the second diode structure, the first PMOS transistor and the second PMOS transistor are configured as the second current mirror structure, and the second PMOS transistor and the second NMOS transistor are configured as the second inverter with the input terminal and the output terminal connected to each other.

3 . The sense amplifier of claim 2 , wherein the control circuit comprises:
a first switch, a first terminal of the first switch being connected to a gate of the first PMOS transistor, and a second terminal of the first switch being connected to a gate of the second PMOS transistor; a second switch, a first terminal of the second switch being connected to the gate of the second PMOS transistor, and a second terminal of the second switch being connected to the first node; a third switch, a first terminal of the third switch being connected to the second node, and a second terminal of the third switch being connected to the gate of the first PMOS transistor; a fourth switch, a first terminal of the fourth switch being connected to the first node, and a second terminal of the fourth switch being connected to the first bit line; and a fifth switch, a first terminal of the fifth switch being connected to the second bit line, and a second terminal of the fifth switch being connected to the second node; wherein in the case of reading the data in the memory cell on the first bit line, at the offset compensation stage of the sense amplifier, the first switch, the second switch, the fourth switch and the fifth switch are turned on, and the third switch is turned off; in the case of reading the data in the memory cell on the second bit line, at the offset compensation stage of the sense amplifier, the first switch, the third switch, the fourth switch and the fifth switch are turned on, and the second switch is turned off.

4 . The sense amplifier of claim 3 , wherein at the offset compensation stage of the sense amplifier, a source of the first PMOS transistor and a source of the second PMOS transistor receive a first voltage, and a source of the first NMOS transistor and a source of the second NMOS transistor are grounded.

5 . The sense amplifier of claim 4 , wherein in the case of reading the data in the memory cell on the first bit line, at a first amplification stage of the sense amplifier, the control circuit is arranged to configure the amplification circuit as a third inverter.

6 . The sense amplifier of claim 5 , wherein in the case of reading the data in the memory cell on the first bit line, at the first amplification stage of the sense amplifier, the second PMOS transistor and the second NMOS transistor are controlled to be in a cutoff region, and the first PMOS transistor and the first NMOS transistor are configured as the third inverter.

7 . The sense amplifier of claim 4 , wherein in the case of reading the data in the memory cell on the second bit line, at a first amplification stage of the sense amplifier, the control circuit is arranged to configure the amplification circuit as a fourth inverter.

8 . The sense amplifier of claim 7 , wherein in the case of reading the data in the memory cell on the second bit line, at the first amplification stage of the sense amplifier, the first PMOS transistor and the first NMOS transistor are controlled to be in a cutoff region, and the second PMOS transistor and the second NMOS transistor are configured as the fourth inverter.

9 . The sense amplifier of claim 5 , wherein the control circuit further comprises:
a sixth switch, a first terminal of the sixth switch being connected to the second node, and a second terminal of the sixth switch being connected to the first bit line; and a seventh switch, a first terminal of the seventh switch being connected to the second bit line, and a second terminal of the seventh switch being connected to the first node; wherein at the offset compensation stage of the sense amplifier, the sixth switch and the seventh switch are turned off; and at the first amplification stage of the sense amplifier, the first switch, the fourth switch and the fifth switch are turned off, and the second switch, the third switch, the sixth switch and the seventh switch are turned on.

10 . The sense amplifier of claim 6 , wherein in the case of reading the data in the memory cell on the first bit line, at the first amplification stage of the sense amplifier, the source of the first PMOS transistor receives the first voltage, the source of the first NMOS transistor is grounded, and the source of the second PMOS transistor and the source of the second NMOS transistor receive a second voltage; and
wherein the second voltage is less than the first voltage.

11 . The sense amplifier of claim 8 , wherein in the case of reading the data in the memory cell on the second bit line, at the first amplification stage of the sense amplifier, the source of the second PMOS transistor receives the first voltage, the source of the second NMOS transistor is grounded, and the source of the first PMOS transistor and the source of the first NMOS transistor receive a second voltage; and
wherein the second voltage is less than the first voltage.

12 . The sense amplifier of claim 9 , wherein at a second amplification stage after the first amplification stage of the sense amplifier, the control circuit is arranged to configure the amplification circuit as a cross-coupled amplifica

Assignees

• Univ Anhui
• Changxin Memory Tech Inc

Inventors

• Lu Wenjuan
• Ge Junlin
• He Jun
• Ying Zhan
• Li Xin
• Cao Kanyu
• Peng Chunyu
• Lin Zhiting
• Wu Xiulong
• Chen Junning

Classifications

• G11C11/4091 Primary

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title

• G11C11/4094

  Bit-line management or control circuits · CPC title

• G11C7/065

  Differential amplifiers of latching type · CPC title

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C11/4096

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title