Semiconductor device

Patent metadata

Field	Value
Publication number	US-2022044993-A1
Application number	US-202117503723-A
Country	US
Kind code	A1
Filing date	Oct 18, 2021
Priority date	Nov 28, 2019
Publication date	Feb 10, 2022
Grant date	—

Abstract

A semiconductor device including an interlayer insulating layer on a substrate; a conductive line on the interlayer insulating layer; and a contact plug penetrating the interlayer insulating layer, the contact plug being connected to the conductive line, wherein the contact plug includes an upper pattern penetrating an upper region of the interlayer insulating layer, the upper pattern protruding upwardly from a top surface of the interlayer insulating layer, the upper pattern includes a first portion penetrating the upper region of the interlayer insulating layer; and a second portion protruding upwardly from the top surface of the interlayer insulating layer, and a width of a lower region of the second portion in a direction parallel to a top surface of the substrate is greater than a width of an upper region of the second portion in the direction parallel to the top surface of the substrate.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
an interlayer insulating layer on a substrate; a conductive line on the interlayer insulating layer; and a contact plug penetrating the interlayer insulating layer, the contact plug being connected to the conductive line, wherein: the contact plug includes:
a lower pattern penetrating a lower region of the interlayer insulating layer,
an upper pattern penetrating an upper region of the interlayer insulating layer, the lower pattern being connected to the upper pattern; and
a barrier pattern between the lower pattern and the interlayer insulating layer
the upper pattern covers a topmost surface of the barrier pattern and includes a protrusion protruding upwardly from a top surface of the interlayer insulating layer, the protrusion has a width in a direction parallel to a top surface of the substrate, and a width of a lower region of the protrusion is greater than a width of an upper region of the protrusion.

2 . The semiconductor device as claimed in claim 1 , wherein:
the upper pattern includes a first metal, and the lower pattern includes a second metal different from the first metal.

3 . The semiconductor device as claimed in claim 1 , wherein the upper pattern and the lower pattern include a same metal.

4 . The semiconductor device as claimed in claim 1 , wherein the lower pattern is in direct contact with the upper pattern.

5 . The semiconductor device as claimed in claim 1 , wherein the topmost surface of the barrier pattern is located at a lower height from the substrate than or substantially the same height as a topmost surface of the lower pattern.

6 . The semiconductor device as claimed in claim 1 , wherein the topmost surface of the barrier pattern is located at a higher height from the substrate than a topmost surface of the lower pattern and is located at a lower height from the substrate than the top surface of the interlayer insulating layer.

7 . The semiconductor device as claimed in claim 1 , wherein the barrier pattern extends between at least a portion of the upper pattern and the interlayer insulating layer.

8 . The semiconductor device as claimed in claim 1 , wherein:
the conductive line includes:
a line pattern extending in one direction on the interlayer insulating layer; and
a line barrier pattern between the line pattern and the interlayer insulating layer,
a topmost surface of the protrusion is located at a higher height from the substrate than the top surface of the interlayer insulating layer, and the line barrier pattern extends from the top surface of the interlayer insulating layer onto the topmost surface of the protrusion.

9 . A semiconductor device, comprising:
an interlayer insulating layer on a substrate; a conductive line on the interlayer insulating layer; and a contact plug penetrating the interlayer insulating layer, the contact plug being connected to the conductive line, wherein: the contact plug includes a protrusion protruding upwardly from a top surface of the interlayer insulating layer, the conductive line includes:
a line pattern extending in one direction on the interlayer insulating layer; and
a line barrier pattern between the line pattern and the interlayer insulating layer,
a topmost surface of the protrusion is located at a higher height from the substrate than the top surface of the interlayer insulating layer, and the line barrier pattern extends from the top surface of the interlayer insulating layer onto the topmost surface of the protrusion.

10 . The semiconductor device as claimed in claim 9 , wherein:
the protrusion has a width in a direction parallel to a top surface of the substrate, and a width of a lower region of the protrusion is greater than a width of an upper region of the protrusion.

11 . The semiconductor device as claimed in claim 10 , wherein the lower region of the protrusion extends on the top surface of the interlayer insulating layer.

12 . The semiconductor device as claimed in claim 10 , wherein the width of the protrusion becomes progressively lower from a bottom of the protrusion toward a top of the protrusion.

13 . The semiconductor device as claimed in claim 9 , wherein the contact plug includes:
an upper pattern penetrating an upper region of the interlayer insulating layer, the upper pattern including the protrusion; a lower pattern penetrating a lower region of the interlayer insulating layer, the lower pattern being connected to the upper pattern; and a barrier pattern between the lower pattern and the interlayer insulating layer.

14 . The semiconductor device as claimed in claim 13 , wherein the upper pattern covers a topmost surface of the barrier pattern.

15 . The semiconductor device as claimed in claim 14 , wherein the topmost surface of the barrier pattern is located at a lower height from the substrate than or substantially the same height as a topmost surface of the lower pattern.

16 . The semiconductor device as claimed in claim 14 , wherein the topmost surface of the barrier pattern is located at a higher height from the substrate than a topmost surface of the lower pattern and is located at a lower height from the substrate than the top surface of the interlayer insulating layer.

17 . The semiconductor device as claimed in claim 14 , wherein the barrier pattern extends between at least a portion of the upper pattern and the interlayer insulating layer.

18 . A semiconductor device, comprising:
an active fin on a substrate, the active fin including a plurality of semiconductor patterns spaced apart from each other in a first direction perpendicular to a top surface of the substrate; a gate electrode on the active fin, the gate electrode covering a topmost surface of the active fin and extends between the plurality of semiconductor patterns; an interlayer insulating layer on the gate electrode; a conductive line on the interlayer insulating layer; and a contact plug penetrating the interlayer insulating layer, the contact plug being connected to the conductive line, wherein: the contact plug includes a protrusion protruding upwardly from a top surface of the interlayer insulating layer, and the protrusion has a width in a second direction parallel to the top surface of the substrate, and a width of a lower region of the protrusion is greater than a width of an upper region of the protrusion.

19 . The semiconductor device as claimed in claim 18 , wherein the lower region of the protrusion extends on the top surface of the interlayer insulating layer.

20 . The semiconductor device as claimed in claim 18 , further comprising;
source/drain patterns spaced apart from each other in the second direction with the active fin therebetween; a first interlayer insulating layer covering the gate electrode and the source/drain patterns; a second interlayer insulating layer on the first interlayer insulating layer; and a lower contact plug at a side of the gate electrode, the lower contact plug penetrating the first and second interlayer insulating layers and being electrically connected to a corresponding one of the source/drain patterns, wherein the interlayer insulating layer is on the second interlayer insulating layer, and wherein the contact plug penetrates the interlayer insulating layer and is electrically connected to the lower contact plug.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Seo Donghee
• Lee Heonbok
• Kim Tae-Yeol
• Kim Daeyong
• Lee Dohyun

Classifications

• H10W20/4437

  the principal metal being a transition metal · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/4441

  the principal metal being a refractory metal · CPC title

• H10W20/4403

  based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence) · CPC title