Device and method for operating the same

Patent metadata

Field	Value
Publication number	US-2022029414-A1
Application number	US-202016936236-A
Country	US
Kind code	A1
Filing date	Jul 22, 2020
Priority date	Jul 22, 2020
Publication date	Jan 27, 2022
Grant date	—

Abstract

A device is disclosed herein. The device includes an electrostatic discharge (ESD) detector, a bias generator, and an ESD driver including at least two transistors coupled to each other in series. The ESD detector is configured to detect an input signal and generate a detection signal in response to an ESD event being detected. The bias generator is configured to generate a bias signal according to the detection signal. The at least two transistors are controlled according to the bias signal and a logic control signal, and the input signal is applied across the at least two transistors.

First claim

1 . A device, comprising:
an electrostatic discharge (ESD) detector configured to detect an input signal and generate a detection signal in response to an ESD event being detected; a bias generator comprising a transistor configured to receive the detection signal and a reference voltage signal, wherein the transistor is configured to transmit, in response to the detection signal, the reference voltage signal as a bias signal; and an ESD driver comprising at least two transistors coupled to each other in series, wherein the at least two transistors are controlled according to the bias signal and a logic control signal, and the input signal is applied across the at least two transistors.

2 . The device of claim 1 , wherein a first terminal of the at least two transistors is configured to receive the input signal, and a second terminal of the at least two transistors is grounded or configured to receive a power supply voltage, wherein the reference voltage signal has a ground voltage or the power supply voltage.

3 . The device of claim 2 , wherein a first transistor of the at least two transistors is controlled according to the logic control signal, and a second transistor of the at least two transistors is controlled according to the bias signal, wherein a first voltage across the first transistor and a second voltage across the second transistor are substantially the same.

4 . The device of claim 1 , wherein the ESD driver comprises:
a first transistor configured to receive the input signal; and a second transistor coupled to the first transistor in series; wherein the input signal is applied to the first transistor and the second transistor equally.

5 . The device of claim 4 , wherein the ESD driver further comprises:
a third transistor coupled to the second transistor in series; wherein the input signal is applied to the first transistor, the second transistor and the third transistor equally.

6 . The device of claim 4 , wherein the first transistor is controlled according to the logic control signal, and the second transistor is controlled according to the bias signal.

7 . The device of claim 6 , further comprising:
a transmission gate configured to provide the logic control signal to the first transistor, wherein the transmission gate stops providing the logic control signal to the first transistor in response to the ESD event being detected.

8 . The device of claim 7 , further comprising:
a secondary bias generator configured to provide a secondary bias signal to the first transistor in response to the ESD event being detected so that a first voltage across the first transistor and a second voltage across the second transistor are substantially the same.

9 . A device, comprising:
a pad configured to receive an input signal; an ESD protection circuit coupled to the pad; an ESD detector coupled to the pad, configured to detect the input signal, and configured to generate a detection signal in response to an ESD event being detected; a bias generator coupled to the ESD detector and comprising a transistor configured to receive the detection signal and a reference voltage signal, wherein the transistor is configured to transmit, in response to the detection signal, the reference voltage signal as a bias signal; and an ESD driver comprising a plurality of transistors coupled to each other in series, wherein when the ESD event occurs, the plurality of transistors are controlled according to the bias signal and a logic control signal so that voltage drops across each transistor of the plurality of transistors are substantially the same.

10 . The device of claim 9 , wherein the ESD detector comprises:
at least two diodes coupled to each other at an input terminal; and a RC circuit coupled to the at least two diodes in parallel, comprising:
a resistor; and
a capacitor coupled to the resistor at an output terminal;
wherein the input terminal is configured to receive the input signal, and the output terminal is configured to generate the detection signal when the ESD event occurs.

11 . The device of claim 10 , wherein a first transistor of the plurality of transistors of the ESD driver is coupled to the pad, and a second transistor of the plurality of transistors of the ESD driver is grounded or coupled to a power supply.

12 . The device of claim 11 , wherein when the ESD event occurs, the first transistor is turned off according to the logic control signal, and the second transistor is turned off according to the bias signal so that a first voltage drop across the first transistor and a second voltage drop across the second transistor are substantially the same.

13 . The device of claim 12 , further comprising:
a transmission gate coupled to the first transistor and configured to provide the logic control signal to the first transistor, wherein when the ESD event occurs, the transmission gate is turned off according to the detection signal, and the transmission gate stops providing the logic control signal to the first transistor.

14 . The device of claim 13 , further comprising:
a secondary bias generator configured to provide a secondary bias signal to the first transistor when the ESD event occurs so that the first voltage drop across the first transistor and the second voltage drop across the second transistor are substantially the same.

15 . A method, comprising:
generating a detection signal in response to an ESD event being detected; receiving, by a transistor, the detection signal and a reference voltage signal; transmitting, by the transistor, the reference voltage signal as a bias signal in response to the detection signal; and controlling at least two transistors of an ESD driver according to the bias signal and a logic control signal, wherein an input signal is applied across the at least two transistors.

16 . The method of claim 15 , wherein a first terminal of the at least two transistors is configured to receive the input signal, and a second terminal of the at least two transistors is grounded or configured to receive a power supply voltage, wherein the reference voltage signal has a ground voltage or the power supply voltage.

17 . The method of claim 16 , wherein controlling the at least two transistors of the ESD driver according to the bias signal and the logic control signal comprises:
controlling a first transistor of the at least two transistors according to the logic control signal; and controlling a second transistor of the at least two transistors according to the bias signal.

18 . The method of claim 17 , wherein controlling the at least two transistors of the ESD driver according to the bias signal and the logic control signal further comprises:
controlling a third transistor of the ESD driver, wherein the input signal is applied to the first transistor, the second transistor and the third transistor equally.

19 . The method of claim 17 , further comprising:
providing the logic control signal to the first transistor; and stopping providing the logic control signal to the first transistor in response to the ESD event being detected.

20 . The method of claim 19 , further comprising:
providing a secondary bias signal to the first transistor in response to the ESD event being detected so that a first voltage across the first transistor and a second voltage across the second transistor are substantially the same.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Peng Po-Lin
• Su Yu-Ti
• Hsu Chia-Wei
• Tsai Ming-Fu
• Su shu-yu
• Chu Li-Wei
• Lee Jam-Wem
• Chang Chia-Jung
• Cheng Hsiang-Hui

Classifications

• H10D89/931

  characterised by the dispositions of the protective arrangements · CPC title

• H10D89/819 Primary

  Bias arrangements for gate electrodes of FETs, e.g. RC networks or voltage partitioning circuits (FETs in a Darlington configuration H10D89/817) · CPC title

• H10D89/60 Primary

  Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] · CPC title

• G01R31/001

  Measuring interference from external sources to, or emission from, the device under test, e.g. EMC, EMI, EMP or ESD testing (measuring electromagnetic fields G01R29/08; circuits for generating HV pulses in dielectric strength testing G01R31/14) · CPC title

• H03K19/00361

  in field effect transistor circuits · CPC title