Electrostatic discharge protection circuit

Patent metadata

Field	Value
Publication number	US-9190840-B2
Application number	US-201313956333-A
Country	US
Kind code	B2
Filing date	Jul 31, 2013
Priority date	Feb 12, 2010
Publication date	Nov 17, 2015
Grant date	Nov 17, 2015

Abstract

An electrostatic discharge (ESD) protection circuit, suitable for an input stage circuit including a first N channel metal oxide semiconductor (NMOS) transistor, is provided. The ESD protection circuit includes an P channel metal oxide semiconductor (PMOS) transistor and an impedance device, in which the PMOS transistor has a source coupled to a gate of the first NMOS transistor, and a drain coupled to a source of the first NMOS transistor, and the impedance device is coupled between a gate of the PMOS transistor and a first power rail to perform a initial-on ESD protection circuit. The ESD protection circuit formed by the PMOS transistor and the resistor is capable of increasing the turn-on speed of the ESD protection circuit and preventing the input stage circuit from a CDM ESD event.

First claim

What is claimed is:

1. An electrostatic discharge (ESD) protection circuit, suitable for an input stage circuit including a first N-channel metal oxide semiconductor (NMOS) transistor, the ESD protection circuit comprising:
a P-channel metal oxide semiconductor (PMOS) transistor having a source directly coupled to a gate of the first NMOS transistor, and a drain directly coupled to a source of the first NMOS transistor;
an impedance device, coupled to the gate of the PMOS trans…

Assignees

• United Microelectronics Corp
• Univ Nat Chiao Tung

Inventors

• Ker Ming-Dou
• Lin Chun-Yu
• Wang Chang-Tzu

Classifications

• H02H9/046 Primary

  Electricity · mapped topic

• H10D89/819 Primary

  Electricity · mapped topic

• H01L27/0285

  Electricity · mapped topic