Apparatuses comprising vertical transistors having gate electrodes at least partially recessed within channel regions, and related methods and systems

Patent metadata

Field	Value
Publication number	US-2022029015-A1
Application number	US-202016936983-A
Country	US
Kind code	A1
Filing date	Jul 23, 2020
Priority date	Jul 23, 2020
Publication date	Jan 27, 2022
Grant date	—

Abstract

An apparatus includes at least one vertical transistor having a channel region. The channel region includes an upper region having a first width and a lower region below the upper region and having a second width smaller than the first width. The upper region defines at least one overhang portion extending laterally beyond the lower region. The at least one vertical transistor further includes gate electrodes at least partially vertically beneath the at least one overhang portion of the upper region of the channel region. Additional apparatuses and related systems and methods are also disclosed.

First claim

1 . An apparatus, comprising:
at least one vertical transistor, comprising:
a channel region comprising:
an upper region having a first width; and
a lower region below the upper region and having a second width smaller than the first width, and
wherein the upper region defines at least one overhang portion extending laterally beyond the lower region; and

gate electrodes at least partially vertically beneath the at least one overhang portion of the upper region of the channel region.

2 . The apparatus of claim 1 , wherein sidewalls of the upper region and sidewalls of the lower region are substantially vertical.

3 . The apparatus of claim 1 , wherein the at least one vertical transistor comprises:
a first vertical transistor having a first gate electrode, electrode; and an adjacent second vertical transistor having a second gate electrode.

4 . The apparatus of claim 3 , further comprising an insulative material between the first gate electrode of the first vertical transistor and the second gate electrode of the second vertical transistor.

5 . The apparatus of claim 3 , further comprising an air gap between the first gate electrode of the first vertical transistor and the second gate electrode of the second vertical transistor.

6 . The apparatus of claim 5 , wherein at least a portion of the air gap is laterally adjacent to the lower region of the channel region.

7 . The apparatus of claim 5 , wherein at least a portion of the air gap is laterally adjacent to the upper region of the channel region.

8 . The apparatus of claim 1 , wherein the gate electrodes are laterally adjacent the lower region of the channel region.

9 . The apparatus of claim 1 , wherein the gate electrodes are at least partially recessed into the lower region of the channel region.

10 . The apparatus of claim 1 , wherein a ratio of the second width of the lower region of the channel region and the first width of the upper region of the channel region is between 0.25 and 0.85.

11 . The apparatus of claim 1 , further comprising a conductive material over the upper region of the channel region and another conductive material below the lower region of the channel region.

12 . The apparatus of claim 1 , wherein a distance by which the at least one overhang portion of the upper region extends over a gate electrode of the gate electrodes is at least one-third of an overall width of the gate electrode.

13 . The apparatus of claim 1 , wherein a distance by which the at least one overhang portion of the upper region extends over a gate electrode of the gate electrodes is at least one-half of an overall width of the gate electrode.

14 . The apparatus of claim 1 , wherein a distance by which the at least one overhang portion of the upper region extends over a gate electrode of the gate electrodes is at least two-thirds of an overall width of the gate electrode.

15 . The apparatus of claim 1 , wherein a gate electrode of the gate electrodes is substantially completely disposed vertically beneath the at least one overhang portion of the upper region of the channel region.

16 . The apparatus of claim 1 , further comprising a gate dielectric material between the gate electrodes and the at least one overhang portion of the upper region and between the gate electrodes and the lower region of the channel region.

17 . A method of forming an apparatus, the method comprising:
removing portions of a channel material to form one or more channel regions separated by trenches; forming a liner material over bottom surfaces of the trenches and over sidewalls of the one or more channel regions; removing portions of the liner material from horizontal surfaces of the one or more channel regions; removing exposed portions of the channel material to form elongated trenches; removing portions of the channel material below the liner material without substantially removing the liner material to form upper regions of the channel regions and lower regions of the channel regions, each upper region defining at least one overhang portion extending outward beyond an outer boundary of a respective lower region; forming a gate dielectric material over the sidewalls of the lower regions and at least the at least one overhang portion of each of the upper regions of the channel regions; and forming gate electrodes adjacent to the gate dielectric material, at least a portion of each gate electrode being beneath a respective overhang portion of a respective upper region of the one or more channel regions.

18 . The method of claim 17 , further comprising:
forming a spacer material on bottom surfaces of the elongated trenches; forming the gate dielectric material over the spacer material, the lower regions of the one or more channel regions, and the upper regions of the one or more channel regions; forming a gate electrode material over the gate dielectric material within the elongated trenches; forming recesses through the gate electrode material to expose the spacer material; forming an insulative material in the recesses and over the bottom surfaces of the elongated trenches; removing portions of the gate dielectric material and the gate electrode material horizontally adjacent to the upper regions of the one or more channel regions; and forming additional insulative material within the elongated trenches.

19 . The method of claim 17 , wherein removing at least some of the liner material overlaying sidewalls of the one or more channel regions and portions of the channel material vertically beneath the liner material overlaying sidewalls of the one or more channel regions in substantially a horizontal direction via an isotropic etch comprises removing the channel material at a greater rate than the liner material.

20 . The method of claim 17 , further comprising:
forming a spacer material on bottom surfaces of the elongated trenches; forming the gate dielectric material over the spacer material, the lower regions of the one or more channel regions, and the upper regions of the one or more channel regions; forming a gate electrode material over the gate dielectric material within the elongated trenches; forming recesses through the gate electrode material to expose the spacer material; forming additional spacer material within the recesses; removing portions of the gate dielectric material, the gate electrode material, and the spacer material horizontally adjacent to the upper regions of the one or more channel regions; removing remaining portions of the spacer material within the elongated trenches; and forming additional insulative material within a portion of the elongated trenches, an additional portion of the elongated trenches adjacent to the lower regions of the channel regions comprising an air gap.

21 . An apparatus, comprising:
at least one vertical transistor, comprising:
a channel region:
gate electrodes at least partially recessed within the channel region relative to an outermost surface of the channel region in a direction orthogonal to a longitudinal axis of the at least one vertical transistor; and
a gate dielectric material between the gate electrodes and the channel region.

22 . The apparatus of claim 21 , wherein a distance by which each gate electrode of the gate electrodes is recessed within the channel region relative to an outermost surface of the channel region is at least one-half of an overall width of the gate electrode in the direction orthogonal to the l

Assignees

• Micron Technology Inc

Inventors

• Simsek-Ege Fatma Arzum
• Torek Kevin J
• Karda Kamal M
• Gao Yunfei
• Muthukrishnan Kamal K

Classifications

• H10D84/837

  comprising vertical IGFETs · CPC title

• H10D84/0151

  Manufacturing their isolation regions · CPC title

• H10W10/021

  of air gaps · CPC title

• H10W10/20

  Air gaps · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title