Electronic devices comprising memory pillars and dummy pillars including an oxide material, and related systems and methods

US2022028881A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2022028881-A1
Application numberUS-202016937303-A
CountryUS
Kind codeA1
Filing dateJul 23, 2020
Priority dateJul 23, 2020
Publication dateJan 27, 2022
Grant date

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

An electronic device comprising lower and upper decks adjacent to a source. The lower and upper decks comprise tiers of alternating conductive materials and dielectric materials. Memory pillars in the lower and upper decks are configured to be operably coupled to the source. The memory pillars comprise contact plugs in the upper deck, cell films in the lower and upper decks, and fill materials in the lower and upper decks. The cell films in the upper deck are adjacent to the contact plugs and the fill materials in the upper deck are adjacent to the contact plugs. Dummy pillars are in a central region of the lower deck and the upper deck. The dummy pillars comprise an oxide material in the upper deck, the oxide material contacting the contact plugs and the fill materials. Additional electronic devices and related systems and methods are also disclosed.

First claim

Opening claim text (preview).

What is claimed is: 1 . An electronic device, comprising: a lower deck and an upper deck adjacent to a source, each of the lower deck and the upper deck comprising tiers of alternating conductive materials and dielectric materials; memory pillars in the lower deck and in the upper deck, the memory pillars configured to be operably coupled to the source and comprising: contact plugs in the upper deck; cell films in the lower deck and in the upper deck, the cell films in the upper deck adjacent to the contact plugs; and fill materials in the lower deck and in the upper deck, the fill materials in the upper deck adjacent to the contact plugs; and dummy pillars in a central region of the lower deck and the upper deck, the dummy pillars comprising an oxide material in the upper deck and the oxide material contacting the contact plugs and the fill materials. 2 . The electronic device of claim 1 , wherein the memory pillars extend through the upper deck and the lower deck. 3 . The electronic device of claim 1 , wherein the memory pillars extend through the upper deck, the lower deck, and into the source. 4 . The electronic device of claim 1 , wherein the oxide material of the dummy pillars extends partially through the upper deck. 5 . The electronic device of claim 1 , wherein the dummy pillars further comprise additional contact plugs, additional cell films, and additional fill materials adjacent to the oxide material. 6 . The electronic device of claim 5 , wherein the additional contact plugs and the additional fill materials of the dummy pillars directly contact the oxide material. 7 . The electronic device of claim 5 , wherein sidewalls of the additional fill materials are sloped. 8 . The electronic device of claim 5 , wherein an upper surface of the additional fill materials is substantially coplanar to an upper surface of the cell films. 9 . The electronic device of claim 5 , wherein the oxide material of the dummy pillars separates the additional contact plugs into two portions. 10 . The electronic device of claim 5 , wherein the oxide material of the dummy pillars separates the additional fill materials into two portions. 11 . The electronic device of claim 1 , wherein the tiers comprise alternating tungsten materials and silicon oxide materials. 12 . An electronic device, comprising: memory pillars in decks of an electronic device, the memory pillars configured to be operably coupled to a source; and dummy pillars in a central region of the decks, the dummy pillars comprising an oxide material in an upper portion of the dummy pillars and the oxide material comprising a substantially continuous material extending between adjacent dummy pillars in the central region. 13 . The electronic device of claim 12 , wherein the dummy pillars further comprise contact plugs and fill materials, the contact plugs and the fill materials comprising multiple portions and each portion on an opposing surface of the oxide material. 14 . The electronic device of claim 13 , wherein the oxide material extends continuously between adjacent contact plugs of the dummy pillars. 15 . The electronic device of claim 12 , wherein the decks comprises a lower deck and an upper deck adjacent to the source, each of the lower deck and the upper deck comprising tiers of alternating conductive materials and dielectric materials. 16 . The electronic device of claim 12 , wherein the oxide material electrically isolates the dummy pillars from the source. 17 . The electronic device of claim 12 , wherein a critical dimension of the dummy pillars is substantially the same as a critical dimension of the memory pillars. 18 . An electronic device, comprising: memory pillars in decks of an electronic device, the memory pillars configured to be operably coupled to a source; and dummy pillars in a central region of the decks, the dummy pillars comprising an oxide material, contact plugs, and fill materials in an upper portion of the dummy pillars and the dummy pillars exhibiting a critical dimension that is substantially the same as a critical dimension of the memory pillars. 19 . A system comprising: an input device; an output device; a processor device operably coupled to the input device and the output device; and at least one memory device operably coupled to the processor device, the at least one memory device comprising: memory pillars in decks of the at least one memory device, the memory pillars comprising contact plugs and cell films operably coupled to a source; and dummy pillars in the decks, the dummy pillars comprising an oxide material in an upper portion thereof and the oxide material isolating conductive portions of the dummy pillars from the source. 20 . The system of claim 19 , wherein the oxide material of the dummy pillars directly contacts contact plugs and fill materials of the dummy pillars. 21 . The system of claim 20 , wherein an upper surface of the oxide material is substantially coplanar with an upper surface of the contact plugs. 22 . The system of claim 20 , wherein opposing sides of the oxide material directly contact the contact plugs. 23 . The system of claim 20 , wherein the oxide material separates the contact plugs of the dummy pillars into two portions. 24 . The system of claim 19 , wherein the cell films of the memory pillars comprise a channel material and one or more cell materials. 25 . The system of claim 19 , wherein the decks are vertically adjacent to one another. 26 . The system of claim 19 , wherein the oxide material comprises a low quality oxide material. 27 . A method of forming an electronic device, comprising: forming a lower deck comprising lower pillars in tiers of alternating nitride materials and dielectric materials adjacent to a source; forming an upper deck comprising additional tiers of alternating nitride materials and dielectric materials adjacent to the lower deck; forming pillar openings in the upper deck; forming upper pillars in the pillar openings, the upper pillars comprising contact plugs, cell films, and fill materials; removing a portion of the contact plugs and fill materials from the upper pillars in a central region of the upper deck to form central openings; forming an oxide material in the central openings of the central region of the upper deck; and replacing the nitride materials of the tiers and of the additional tiers with conductive materials. 28 . The method of claim 27 , wherein forming a lower deck comprising lower pillars in tiers of alternating nitride materials and dielectric materials comprises forming additional pillar openings in the tiers of the lower deck and forming additional cell films and additional fill materials in the additional pillar openings. 29 . The method of claim 27 , wherein forming upper pillars in the pillar openings comprises substantially aligning the upper pillars with the lower pillars. 30 . The method of claim 27 , wherein removing a portion of the contact plugs and fill materials from the upper pillars to form central openings comprises forming the central openings defined by substantially sloped sidewalls of the contact plugs and the fill materials. 31 . The method of claim 30 , wherein forming the central openings defined by substantially sl

Assignees

Inventors

Classifications

  • by forming openings in the dielectric parts · CPC title

  • by forming self-aligned vias or self-aligned contact plugs · CPC title

  • by filling conductive material into holes, grooves or trenches · CPC title

  • Electricity · mapped topic

  • Electricity · mapped topic

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US2022028881A1 cover?
An electronic device comprising lower and upper decks adjacent to a source. The lower and upper decks comprise tiers of alternating conductive materials and dielectric materials. Memory pillars in the lower and upper decks are configured to be operably coupled to the source. The memory pillars comprise contact plugs in the upper deck, cell films in the lower and upper decks, and fill materials …
Who is the assignee on this patent?
Micron Technology Inc
What technology area does this patent fall under?
Primary CPC classification H01L27/11582. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Jan 27 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).