Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2022020686-A1
Application number	US-202117491775-A
Country	US
Kind code	A1
Filing date	Oct 1, 2021
Priority date	Jul 23, 2019
Publication date	Jan 20, 2022
Grant date	—

Abstract

The present technology relates to a semiconductor device and a method of manufacturing the same. The semiconductor device includes a first stack including first interlayer insulating layers and first conductive patterns which are alternately stacked with one another, a second stack including second interlayer insulating layers and second conductive patterns which are alternately stacked with one another on the first stack, a plurality of channel plugs vertically formed through the first stack and the second stack, and at least one dummy plug vertically formed through the second without passing through the first stack.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a first stack including first interlayer insulating layers and first conductive patterns which are alternately stacked with one another; a second stack including second interlayer insulating layers and second conductive patterns which are alternately stacked with one another on the first stack; a plurality of channel plugs at least partially passing through the first stack and the second stack and extending in a vertical direction; at least one dummy plug at least partially passing through the second stack without passing through the first stack; and first and second slits at least partially passing through the first stack and the second stack, wherein the at least one dummy plug is disposed in a region adjacent to the first and second slits.

2 . The semiconductor device of claim 1 , wherein the plurality of channel plugs are regularly arranged to be spaced apart from each other by a predetermined distance.

3 . The semiconductor device of claim 2 , wherein the at least one dummy plug is arranged in an outermost corner region of a region where the plurality of channel plugs are arranged.

4 . The semiconductor device of claim 1 , wherein the plurality of channel plugs and the at least one dummy plug are interposed between the first and second slits.

5 . The semiconductor device of claim 1 , wherein the channel plugs and the at least one dummy plug each comprise:
a gap fill film; a channel film surrounding the gap fill film; and a memory film surrounding the channel film.

6 . The semiconductor device of claim 1 , wherein a lower portion of the at least one dummy plug is in contact with an uppermost film of the first stack.

7 . A semiconductor device comprising:
a first stack including first interlayer insulating layers and first conductive patterns which are alternately stacked with one another; a second stack including second interlayer insulating layers and second conductive patterns which are alternately stacked with one another on the first stack; a plurality of channel plugs at least partially passing through the portion or the entirety of the first stack and the second stack and extending in a vertical direction; at least one dummy plug at least partially passing through the second stack without passing through the first stack; and first and second slits at least partially passing through the portion or the entirety of the first stack and the second stack, wherein the plurality of channel plugs and the at least one dummy plug include same material layers.

8 . The semiconductor device of claim 7 , wherein the plurality of channel plugs are regularly arranged to be spaced apart from each other by a predetermined distance.

9 . The semiconductor device of claim 8 , wherein the at least one dummy plug is arranged in an outermost corner region of a region where the plurality of channel plugs are arranged.

10 . The semiconductor device of claim 7 , wherein the plurality of channel plugs and the at least one dummy plug are interposed between the first and second slits.

11 . The semiconductor device of claim 8 , wherein the channel plugs and the at least one dummy plug each comprise:
a gap fill film; a channel film surrounding the gap fill film; and a memory film surrounding the channel film.

12 . The semiconductor device of claim 8 , wherein a lower portion of the at least one dummy plug is in contact with an uppermost film of the first stack.

Assignees

• Sk Hynix Inc

Inventors

• Park Hae Chan
• Kim Jang Won
• Kim Jae Taek

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/42 Primary

  Vias, e.g. via plugs · CPC title

• H10D30/68

  Floating-gate IGFETs · CPC title

• H10D30/0411

  of FETs having floating gates · CPC title

• H10D30/6891

  characterised by the shapes, relative sizes or dispositions of the floating gate electrode · CPC title